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lmb - 0 Local Memory Bus(LMB v1.0(v1.00a DS445 April 4 2005...

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Local Memory Bus (LMB) v1.0 (v1.00a) DS445 April 4, 2005 0 0 Product Specification DS445 April 4, 2005 www.xilinx.com 1 Product Specification © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction The LMB_V10 module is used as the LMB interconnect for Xilinx FPGA based embedded processor systems. The LMB is a fast, local bus for connecting MicroBlaze™ instruc- tion and data ports to high-speed peripherals, primarily on-chip block RAM (BRAM). Features Efficient, single master bus (requires no arbiter) Separate read and write data buses Low FPGA resource utilization 125 MHz operation LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex™-II, QPro Virtex-II, Spartan™-II, Spartan-IIE, Spartan-3, Virtex, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-E Version of Core lmb_v10 v1.00a Resources Used Min Max Slices
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