opb_arbiter - OPB Arbiter (v1.02e) DS469 September 23, 2005...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: OPB Arbiter (v1.02e) DS469 September 23, 2005 Product Specification DS469 September 23, 2005 www.xilinx.com 1 Product Specification © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen- tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple- mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction The On-Chip Peripheral Bus (OPB) Arbiter design described in this document incorporates the features contained in the IBM On-chip Peripheral Bus Arbiter Core manual (version 1.5) for 32-bit implementation, which is referenced throughout this document and is considered the authoritative specification. Any differences between the IBM OPB Arbiter implementation and the Xilinx OPB Arbiter implementation are explained in the Specification Exceptions section of this document. The Xilinx OPB Arbiter design allows the user to tailor the OPB Arbiter to suit a specific application by setting certain parameters to enable/disable features. In some cases, setting these parameters may cause the Xilinx OPB Arbiter design to deviate slightly from the IBM OPB Arbiter specification. These parameters are described in the OPB Arbiter Design Parameters section of this document. Features • The OPB Arbiter is a soft IP core designed for Xilinx FPGAs and contains the following features: • Optional OPB slave interface (included in design via a design parameter) • OPB Arbitration- arbitrates between 1–16 OPB Masters (the number of masters is parameterizable)- arbitration priorities among masters programmable via register write- priority arbitration mode configurable via a design parameter · Fixed priority arbitration with processor access to read/write Priority Registers · Dynamic priority arbitration implementing a true least recent used (LRU) algorithm LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex™-II, QPro Virtex-II, Spartan™-II, Spartan-IIE, Spartan-3, Virtex, Virtex-II, Virtex-E, Virtex-II Pro, Virtex-4 Version of Core opb_arbiter v1.02e Resources Used Min Max I/O 4 904 LUTs 6 252 FFs 4 1477 Block RAMs Provided with Core Documentation Product Specification Design File Formats VHDL...
View Full Document

This note was uploaded on 11/11/2009 for the course CSE CS taught by Professor Crm during the Spring '08 term at Indian Institute of Technology, Kharagpur.

Page1 / 36

opb_arbiter - OPB Arbiter (v1.02e) DS469 September 23, 2005...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online