web_server_example-settin gin_computer_ip

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Unformatted text preview: Application Note: Virtex-II Pro Family R XAPP433 (v1.0) August 10, 2004 Embedded System Example: Web Server Design Using MicroBlaze Soft Processor Author: Martin Muggli, Matthew Ouellette, Sathyanarayanan Thammanur Summary This application note details an embedded system example design of a web server running on the MicroBlaze™ soft processor, designed using the Embedded Development Kit (EDK). The application note also explains how to set up a system as a web client and how to connect to the web server running on the MicroBlaze processor. Hardware Requirements • Memec 2VP4 Development Board (Rev. 1) with P160 Communications module. The development board contains a Xilinx XC2VP4 Virtex-II Pro™ FPGA. See “Porting the Design to Memec 2VP4 Rev. 2, Rev. 3, or Rev. 4” for information on porting this design to later revisions of the Memec 2VP4 Development Board. • • JTAG Parallel 4 Cable Cross-over Ethernet Cable Software Requirements • • • • Embedded Development Kit (EDK) 6.2 SP2. ISE 6.2i SP2 or later. Internet Explorer, Netscape, or Mozilla web browser. Web server EDK project (downloaded from Xilinx web site). The project can be opened in the Xilinx Platform Studio (XPS), through which the web server design can be customized and downloaded to the Xilinx FPGA. The MicroBlaze web server design can be downloaded from: http://www.xilinx.com/ise/embedded/Memec_v2p.zip Introduction The embedded system design used in this application note contains these components (see Figure 1): • • A MicroBlaze soft processor connected to 8kB of BRAM memory over the Local Memory Bus (LMB). A UARTLite, an external SRAM memory interface, an Ethernet 10/100 MAC, and a General Purpose I/O (GPIO), all connected to the On-chip Peripheral Bus (OPB). All of the IP cores used in the design are described in the Processor IP Reference Guide included with the EDK. In the design, four GPIO output bits are connected to LEDs LED1 – LED4 on the development board and four input GPIO bits are connected to DIP switches DIP1 – DIP4. In the design example, the Ethernet MAC is running at 100 Mb/s. To run the example the peer network connection needs to be set to 100 Mb/s. © 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. XAPP433 (v1.0) August 10, 2004 www.xilinx.com 1-800-255-7778 1 R The Web Server A Fast Simplex Link (FSL) interface provides a fast connection from the OPB MicroBlaze Debug Module (MDM) to the MicroBlaze processor. This download mechanism supports file download speeds up to 500 KB/s. In the xmd.ini script, the ELF file is downloaded using this interface. Note: The 10/100 Ethernet MAC OPB peripheral (OPB_ETHERNET) used with this design is not a free core. To use the core an evaluation license is required; the evaluation license is included with the EDK. The evaluation version of the core includes built-in timeout circuitry which disables the core after a period of time. DLMB Bus FSL Download Link OPB_MDM BRAM_BLOCK LMB_BRAM_IF_CNTLR MICROBLAZE OPB Bus ILMB Bus OPB_GPIO OPB_UARTLITE OPB_ETHERNET OPB_EMC External SRAM x428_01_070104 Figure 1: MicroBlaze Web Server Design Table 1 shows the devices used in the web server design and the memory map for the design. Table 1: Web Server Design Devices Device MICROBLAZE BRAM_BLOCK LMB_BRAM_IF_CNTLR OPB_ETHERNET OPB_EMC OPB_GPIO OPB_UARTLITE OPB_MDM Hardware Version 2.10.a 1.00.a 1.00.b 1.01.a 1.10.b 1.00.a 1.00.b 2.00.a Address MIN N/A N/A 0x0000_0000 0x8000_0000 0x80F0_0000 0xFFFF_0100 0xFFFF_0200 0xFFFF_0300 MAX N/A N/A 0x0000_1FFF 0x8000_3FFF 0x80FF_FFFF 0xFFFF_01FF 0xFFFF_02FF 0xFFFF_03FF Size (Bytes) N/A 8k 8k 16k 1 MB 256 256 256 Comment MicroBlaze Processor Block RAM Local Memory Controller Ethernet MAC External SRAM Memory Controller DIP Switch Input, LED Output Serial I/O Debug Peripheral The Web Server The web server source code is located in the project’s /code directory. The LibXil networking and file system libraries accessed by the web server design are included by LibGen, the Library Generator utility. On this system the web server is running HTTP 1.0. A file system, built using the LibXil Memory File System library, stores the files. The server listens for requests at port 8080. Every request is processed, then replies are served up by the server to the client. 2 www.xilinx.com 1-800-255-7778 XAPP433 (v1.0) August 10, 2004 The Web Server R Operations Performed by the Web Server The web server in the design displays a web page (see Figure 2) through which these operations can be performed: • HEX-digit LED Display When a HEX digit is typed in the web page, it is displayed as a four-digit binary number on the board’s LEDs when the web page is reloaded. • • Changing Colors The background color changes each time the web page is reloaded. DIP Switches Set the board’s DIP switches (DIP1, DIP2, DIP3, DIP4) and a binary value is displayed on the web page when the web page is reloaded. Note: For details on how the web server software design works, see the Web Server Flowchart in Figure 4. Figure 2: Web Page to Control Web Server Operations Opening the Web Server Design To open the web server project in the EDK: 1. Unzip the included design files. The design files are the EDK project files describing the web server. 2. Open the Xilinx Platform Studio (XPS) (Start → Programs → Xilinx Embedded Development Kit → Xilinx Platform Studio). XAPP433 (v1.0) August 10, 2004 www.xilinx.com 1-800-255-7778 3 R The Web Server 3. In XPS, select File → Open Project. The Open Project dialog box appears. 4. Browse to the system.xmp file in the memec_v2p/microblaze directory, then open the system.xmp file in XPS. Generating the Netlist and Implementing the Design To generate the system netlist and implement the hardware design: 1. Generate the netlist by selecting Tools → Generate Netlist in XPS. Observe the progress of the operation in the XPS transcript window. The evaluation license for the 10/100 Ethernet MAC core is used to generate the netlist for that core. 2. Implement the design by selecting Tools → Generate Bitstream in XPS. Observe the progress of the operation in the XPS transcript window. When XPS implements the system, it accesses a UCF constraints file for the Memec 2VP4 board. The UCF file is located in the supplied /data directory. XPS also uses the OPT option file included in the /etc directory. Viewing the Libraries Used in the Design The EDK contains software library support for networking and memory file systems. The web server design running on the MicroBlaze soft processor uses the XilNet networking library and the XilMfs memory file system library. To view the library settings for the web server design: 1. In the System tab of the XPS project view window, double-click System BSP → CPU mblaze. 2. In the Software Platform tab of the Software Platform Settings dialog box, observe the Libraries table at the bottom left corner of the dialog box (see Figure 3). The table indicates that the Xilnet and XilMfs libraries are used in the design. 4 www.xilinx.com 1-800-255-7778 XAPP433 (v1.0) August 10, 2004 The Web Server R Figure 3: Libraries Table in Software Platform Settings Dialog Box Configuring the Web Server and Compiling the Web Server Code The Ethernet MAC requires IP and MAC addresses to be initialized and set in the web server code. In the demonstration EDK project, the IP address must be set for the web server to work properly. To set the web server IP address: 1. In the XPS project view window, open the web.c source file by double-clicking code/web.c, located in the Applications tab, under Project → Sources. 2. Browse to the line xilnet_ip_init("1.2.3.4");. The line numbers of any open text documents are displayed on the lower right-hand side of XPS. 3. In the xilnet_ip_init function call, do one of the following: ♦ Leave the argument set to 1.2.3.4 (which will require you to change your host’s IP address) OR Change the argument to match the local IP address of your host. www.xilinx.com 1-800-255-7778 5 ♦ XAPP433 (v1.0) August 10, 2004 R The Web Server 4. Save the changes to web.c. 5. Select Tools → Build All User Applications to compile the web server design. Downloading the Web Server Code Once the web server code is compiled, the download program must be updated and downloaded to the FPGA. To download the code to the FPGA: 1. In XPS, select Tools → Update Bitstream. In the XPS transcript window, observe that the bitstream is updated by the iMPACT (ISE device configuration) tool. Note: The iMPACT GUI cannot be open when the Update Bitstream command runs. 2. Connect the JTAG Parallel 4 cable from the PC to the Memec 2VP4 board. 3. In XPS, select Tools → Download. The bitstream is downloaded to the development board by the iMPACT tool. When the FPGA device is configured, the DONE light is illuminated on the development board. Configuring the Web Client and Running the Web Server Demo 1. Unplug any Ethernet cable connected to the host PC and connect the crossover Ethernet cable to the PC and to the P160 Ethernet module. The JTAG Parallel 4 cable must also remain connected from the PC to the Memec 2VP4 board. 2. Modify the host PC’s IP address so it is in the same subnet as the web server. To change the PC’s IP address: a. Select Start → Settings → Control Panel on the Windows desktop. b. Double-Click Networking and Dialup. c. Right-click the applicable LAN connection, then select Properties. d. Select Internet Protocol and click Properties. Note: When the PC’s IP address is changed in the following steps, note the original property settings, so the properties can be changed back after performing the demo. e. In the Internet Protocol Properties dialog box, select Use the following IP Address. f. In the IP address box, enter a unique IP address in the same subnet as the one specified for the web server. For example, if the IP address specified for the web server was 1.2.3.4, the IP address of 1.2.3.9 can be entered in the IP Address box. g. Click OK on the Internet Protocol Properties dialog box. h. If a message appears indicating that a subnet mask is missing, Select OK. Select OK again and again. 3. In XPS, select Tools → XMD. This will load the application code via the MicroBlaze Debug Module (MDM) using XMD. The XMD console should display Web Server Running. Note: XMD (Xilinx Microprocessor Debugger) is the EDK debug engine for embedded systems. It includes a TCL environment which allows you to create fully customized debug tools. After launching XMD, it will source xmd.ini if the file is present in the EDK project directory. The xmd.ini file contains a list of TCL commands to run each time XMD runs. 4. Open an HTML browser and point to the URL http://x.x.x.x:8080, where x.x.x.x is the IP address you specified for the web server. Note: If the browser uses a proxy to access the Internet, disable the proxy setting and enable a direct connection to the Internet. 6 www.xilinx.com 1-800-255-7778 XAPP433 (v1.0) August 10, 2004 The Web Server R 5. The web server demo page should appear in the browser (see Figure 2). Follow the instructions to read the DIP switch values and write to the LEDs on the development board. For details on how the web server software design works, see the Web Server Flowchart in Figure 4. Porting the Design to Memec 2VP4 Rev. 2, Rev. 3, or Rev. 4 To port the web server design to the newer Rev. 2, Rev. 3, or Rev. 4 boards, make these two changes: • • Part Change: (Only if Rev 2, 3 or 4 has an xc2vp7 FPGA). Change the part in XPS from xc2vp4 fg456 to xc2vp7 fg456. UCF File Change: NET "ETH_RXD<2>" LOC = "G20"; #LIOA15, Rev1 #NET "ETH_RXD<2>" LOC = "F11"; #LIOA15, Rev2,3, or 4 NET "ETH_MDIO" LOC = "H19"; #LIOA13, Rev1 #NET "ETH_MDIO" LOC = "E11"; #LIOA13, Rev2,3, or 4 XAPP433 (v1.0) August 10, 2004 www.xilinx.com 1-800-255-7778 7 R The Web Server Initialize EMAC, network, and filesystem Create, Bind, Listen on Server Socket for port 8080 Create files on filesystem and fill with HTML Set LEDs Is there a new connection request? Y Are connection status structures already initialized? Y N Mark each connection as free N Add connection to list N Is anything received on this connection? Y Has acknowledgement been received for previous data? Close connection and remove from connection list Y N Has data been received (presumably HTTP request)? Y Query DIP switches N Store HEX value from URL Does URL specify filename? N Set to "index.html" Y Does file exist? Y Load from filesystem N Send 404 FILE NOT FOUND error webpage Y Is file "index.html"? Poke new DIP switch value and new background into buffer N Send Page, close file x428_02_012903 Figure 4: Web Server Flowchart 8 www.xilinx.com 1-800-255-7778 XAPP433 (v1.0) August 10, 2004 Reference Design R Reference Design The MicroBlaze web server design files can be downloaded from: http://www.xilinx.com/ise/embedded/Memec_v2p.zip Revision History The following table shows the revision history for this document. Date 08/10/04 Version 1.0 Revision Initial Xilinx release in Application Note template. XAPP433 (v1.0) August 10, 2004 www.xilinx.com 1-800-255-7778 9 ...
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