06_adding_ip - Adding Your Own IP to the OPB Bus 2004...

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© 2004 Xilinx, Inc. All Rights Reserved Adding Your Own IP to the OPB Bus
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Adding Your Own IP to the OPB Bus - 6 - 2 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Objectives After completing this module, you will be able to: Understand basic OPB bus transactions Differentiate between free and evaluation-based IP delivered in EDK Identify the requirements for integrating your IP List the steps involved in importing peripherals when using the wizard List the limitations of creating peripherals with the wizard
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Adding Your Own IP to the OPB Bus - 6 - 3 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline OPB Bus OPB User Core Templates XPS Directory Structure File Creation: MPD, PAO, BBD IP Delivery in EDK Creating/Importing Peripheral Wizard
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Adding Your Own IP to the OPB Bus - 6 - 4 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Overview The peripherals are connected to the microprocessor by using the data and address buses Xilinx has implemented IBM's CoreConnect bus architecture On-chip Peripheral Bus (OPB) version 2.1 of the CoreConnect architecture is designed for easy connection of on-chip peripheral devices Any custom peripheral that connects to the OPB bus must do the following: Meet the principles of the OPB protocol Meet the requirements of the Platform Generator This allows you to take advantage of the simple automated flow that generates the system-level architecture
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Adding Your Own IP to the OPB Bus - 6 - 5 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Features Platform Generator supports the following features for OPB peripherals, and it is a subset of the OPB v2.1 features Fully synchronous single-clock edge 32-bit address bus, 32-bit data bus Single-cycle transfer of data between the OPB master and the OPB slave Supports master byte enables Supports slave timeout suppress Supports slave retry No three-state drivers required Note that the dynamic bus sizing feature is not supported in OPB v2.1
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Adding Your Own IP to the OPB Bus - 6 - 6 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Features MicroBlaze embedded system
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Adding Your Own IP to the OPB Bus - 6 - 7 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Features IBM PowerPC embedded system
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Adding Your Own IP to the OPB Bus - 6 - 8 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Physical Implementation The OPB bus architecture (v2.0) allows for the addition of peripherals to the system, without changing the existing I/ O on either the OPB arbiter or the other existing peripherals
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Adding Your Own IP to the OPB Bus - 6 - 9 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Interface Signals Platform Generator does the following Counts the number of devices attached to the OPB Instantiates opb_v20 Connects the address bus, data buses, and control and
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This note was uploaded on 11/11/2009 for the course CSE CS taught by Professor Crm during the Spring '08 term at Indian Institute of Technology, Kharagpur.

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06_adding_ip - Adding Your Own IP to the OPB Bus 2004...

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