16_adding_ip - Adding Your Own IP to the OPB Bus This...

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This material exempt per Department of Commerce license exception TSU Adding Your Own IP to the OPB Bus
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Adding IP 2 Objectives After completing this module, you will be able to: Understand basic OPB bus transactions Differentiate between free and evaluation-based IP delivered in EDK Identify the requirements for integrating your IP List the steps involved in importing peripherals when using the wizard Identify the limitations of creating peripherals with the wizard
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Adding IP 3 Outline OPB Bus XPS Directory Structure File Creation: MPD, PAO, BBD IP Delivery in EDK Creating/Importing Peripheral Wizard
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Overview The peripherals are connected to the microprocessor by using the data and address buses Xilinx has implemented IBM's CoreConnect bus architecture On-chip Peripheral Bus (OPB) version 2.1 of the CoreConnect architecture is designed for easy connection of on-chip peripheral devices Any custom peripheral that connects to the OPB bus must do the following: Meet the principles of the OPB protocol Meet the requirements of the Platform Generator This allows you to take advantage of the simple automated flow that generates the system-level architecture
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Features Platform Generator supports the following features for OPB peripherals, and it is a subset of the OPB v2.1 features Fully synchronous single-clock edge 32-bit address bus, 32-bit data bus Single-cycle transfer of data between the OPB master and the OPB slave Supports master byte enables Supports slave timeout suppress Supports slave retry No three-state drivers required Note that the dynamic bus sizing feature is not supported in OPB v2.1
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Features IBM PowerPC embedded system
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Physical Implementation The OPB bus architecture (v2.1) allows for the addition of peripherals to the system, without changing the existing I/O on either the OPB arbiter or the other existing peripherals
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Interface Signals Global OPB slave signals Slave signals <Sln>_xferAck <Sln>_errAck <Sln>_toutSup <Sln>_retry <Sln>_DBus OPB bus signals OPB_select OPB_RNW OPB_BE OPB_seqAddr OPB_Abus OPB_DBus OPB Slave OPB Bus Logic <Sln>_xferAck <Sln>_errAck <Sln>_toutSup <Sln>_retry <Sln>_DBus OPB_select OPB_RNW OPB_BE OPB_seqAddr OPB_ABus OPB_DBus
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Timing Diagram (Read) The OPB master asserts OPB_select, then puts valid OPB_ABus, OPB_BE, and OPB_RNW on the buses The slave completes the transfer by asserting OPB_xferAck, which causes the master to latch data from the data bus on read transfers and de-assert OPB_select <Sln>_xferAck <Sln>_DBus OPB_BE OPB_RNW OPB_ABus OPB_select OPB_CLK Cycles Valid Address Read Valid BE Valid Data 1 2 3 4 5 6 0000-0000 0000-0000
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Timing Diagram (Write) The OPB master asserts OPB_select, then puts valid OPB_ABus, OPB_BE, OPB_RNW, and OPB_DBus on the buses The slave latches the data, then completes the transfer by asserting OPB_xferAck, which causes the master to de-assert OPB_select
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This note was uploaded on 11/11/2009 for the course CSE CS taught by Professor Crm during the Spring '08 term at Indian Institute of Technology, Kharagpur.

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16_adding_ip - Adding Your Own IP to the OPB Bus This...

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