popi - POPi Final Project Report Adam Lehenbauer Alexander...

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POPi Final Project Report Adam Lehenbauer Alexander Robertson Javier Coca Yashket Gupta Embedded Systems Design May 09, 2006 1
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Table of Contents 1. Overview ................................................................................................................. 3 2. Hardware ................................................................................................................ 4 3. Software .................................................................................................................. 8 4. Lessons Learned ..................................................................................................... 9 5. Appendix ................................................................................................................ 11 EtherSend.c .................... 11 main.c .................... 14 JayCam.h .................... 15 POP.c .................... 16 POP.h .................... 18 Terminal.c .................... 19 Terminal.h .................... 21 SRAM_Ehernet.vh dl .................... 22 TestBench.vh dl .................... 33 TCPstack .c .................... 38 2
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1. OVERVIEW POPi project displays a message (SMS) in the video screen of the XESS board, sent from a cellular telephone to an e-mail address. The project was designed to take advantage of both hardware and software resources. In consequence the design was divided in two equally important parts. The Hardware components of the project includes a peripheral which acts as a bridge between the SRAM and Ethernet Chip, as shown in figure Num. 1. The POP project implements the TCP IP, Ethernet and the POP3 technology to read an email message send from a Mobile through a cellular network. The board connects to a remote server using the Ethernet chip, the POP program executes the POP3 commands to check and download messages present on the server. The Bridge takes care of accesses to the Ethernet chip and the SRAM as the TCP/IP and the POP programs are executed from the SRAM the bridge needs to provide sufficient functionality to handle 8,16 and 32 bit access from the microblaze. The Video hardware is taken directly from lab2 with the difference that the data is read from the data block on the SRAM. The TCP/IP stack extracts the data from the email and the microblaze puts it to the video. All the communication between the FPGA and the peripherals will be hosted by the OPB. Figure 1. Hardware block diagram. 3 Ethernet SRAM bridge MicroBlaze FPGA Video SRAM Ethernet SERVER
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The Software that the project will require is a very significant part of its functionality. The two major "subsystems," the video controller and the Ethernet controller, and the software is the communication between them. The SRAM will be transparent to the software and appear only as a base address. Figure 2. Software block diagram. 2. HARDWARE. There are two major parts for the Hardware Part of our Design. 1. BRIDGE – A single peripherals connected to the SRAM and Ethernet forming a BRIDGE that allows the Microblaze to talk to both the Ethernet chip and the SRAM 2. Video – We used the Design of Lab 2 for our video with certain modifications. The Bridge Team JAYCam, from last year's class, was able to successfully use the ethernet controller. Our implementation of the Ethernet was based on theirs. The SRAm fuctionality was implmented in the lab 6 but since our code was large and could not be accomodated on the BRAM we had to provide 8,16 and 32 bit access to the SRAM, as C program could call functions which might require such accesses.
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