CSE361S-IntelP6VM - Intel P6 Internal Designation for...

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Page 1 Intel P6 Internal Designation for Successor to Pentium ± Which had internal designation P5 Fundamentally Different from Pentium ± Out-of-order, superscalar operation ± Designed to handle server applications z Requires high performance memory system –1– Resulting Processors ± PentiumPro (1996) ± Pentium II (1997) z Incorporated MMX instructions » special instructions for parallel processing z L2 cache on same chip ± Pentium III (1999) z Incorporated Streaming SIMD Extensions » More instructions for parallel processing P6 Memory System DRAM external system bus (e.g. PCI) L2 cache 32 bit address space 4 KB page size L1, L2, and TLBs ± 4-way set associative inst TLB ± 32 entries ± 8 sets data TLB 64 t i –2– bus interface unit instruction fetch unit L1 i-cache cache bus L1 d-cache inst TLB data TLB processor package ± 64 entries ± 16 sets L1 i L1 i-cache and d cache and d-cache cache ± 16 KB ± 32 B line size ± 128 sets L2 cache ± unified ± 128 KB -- 2 MB Review of Abbreviations Symbols: ± Components of the virtual address (VA) z TLBI: TLB index z TLBT: TLB tag z VPO: virtual page offset z VPN: virtual page number –3– ± Components of the physical address (PA) z PPO: physical page offset (same as VPO) z PPN: physical page number z CO: byte offset within cache line z CI: cache index z CT: cache tag Overview of P6 Address Translation CPU VPN VPO 20 12 TLBT TLBI 4 16 virtual address (VA) TLB result 32 L2 and DRAM L1 (128 sets, 4 lines/set) L1 hit L1 miss –4– ... TLB (16 sets, 4 entries/set) VPN1 VPN2 10 10 PDE PTE PDBR PPN PPO 20 12 Page tables TLB miss hit physical address (PA) ... CT CO 20 5 CI 7 P6 2-level Page Table Structure Page directory ± 1024 4-byte page directory entries (PDEs) that point to page tables ± one page directory per process. ± page directory must be in memory when its process is page directory Up to 1024 page tables 1024 PTEs ... –5– running ± always pointed to by PDBR Page tables: ± 1024 4-byte page table entries (PTEs) that point to pages. ± page tables can be paged in and out. ... 1024 PTEs 1024 PTEs 1024 PDEs P6 Page Directory Entry (PDE) Page table physical base addr Avail G PS A CD WT U/S R/W P=1 Page table physical base address : 20 most significant bits of physical page table address (forces page tables to be 4KB aligned) Avail : These bits available for system programmers G : global page (don’t evict from TLB on task switch) 3 1 1 2 1 1 9876 543210 –6– PS : page size 4K (0) or 4M (1) A : accessed (set by MMU on reads and writes, cleared by software) CD : cache disabled (1) or enabled (0) WT : write-through or write-back cache policy for this page table U/S : user or supervisor mode access R/W : read-only or read-write access P : page table is present in memory (1) or not (0) Available for OS (page table location in secondary storage) P=0 31 0 1
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Page 2 P6 Page Table Entry (PTE) Page physical base address Avail G 0 D A CD WT U/S R/W P=1 Page base address : 20 most significant bits of physical page address (forces pages to be 4 KB aligned) Avail : available for system programmers G : global page (don’t evict from TLB on task switch) 3 1 1 2 1 1 9876 543210
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CSE361S-IntelP6VM - Intel P6 Internal Designation for...

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