hw2 - CSE 422S (Fall 2009) Operating Systems Organization...

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Unformatted text preview: CSE 422S (Fall 2009) Operating Systems Organization Homework 2 Reading: Textbook, Section 2.1, Sections 10.1-10.3 Due: Sep. 16, 2009 Preview: Problems 5 and 6 examine the effects of temporal locality on cache memory performance. Problem 5 should help you understand the output generated in Problem 6 by developing an equation for RWT (Read-Write Time) of an integer which is the approximate time it takes to read an integer, do a simple arithmetic operation on the integer, and then write the new integer back to memory. It also examines the effect of architectural features (e.g., cache line size) on the EMAT. In Problem 6, you compile and run a program that attempts to measure the RWT of an integer. The results should reinforce some of the theoretical analysis done in Problem 5 and begin to give you a sense of typical memory access times and how they are affected by memory reference patterns. Problem 7 should begin to develop your sense of the time required to perform different types of operations (e.g., system calls). It should also develop your skill in using the gettimeofday function to measure the passage of time. Problem 1 Continue to work on Homework 1, Problem 4 if you were unable to complete it on time. Problem 2 (0 Points) [ This is an expanded form from Homework 1. ] If you are unfamiliar with basic Unix, the course web page contains a link to An Introduction to Linux by Machtelt Garrels. I suggest reading Chapters 1, 2, 3 and 6 (if you would rather use the emacs editor instead of vim, use www.google.com to find an emacs tutorial). Chapters 4, 5 and 7 will also be eventually helpful. Problem 3 (0 Points) Consider a 1 GHz CPU that has one instruction pipeline with five (5) stages. Suppose that each stage can execute in one clock cycle when not accessing main memory. a) What is the maximum instruction rate of this machine expressed in MIPS (Millions of In- structions Per Second)? Explain. b) Consider a main memory that causes the CPU to enter the wait state for M clock cycles and a program that must access main memory for data every N instructions. Derive an expression for the MIP rating for the above CPU and memory system. Assume that all instructions following the memory access instruction must wait for the memory operation to complete. Explain how you arrived at your answer. c) Suppose M = 50. For what values of N will the MIP rate in Part b be atleast 50% of its maximum rate found in Part a? Problem 4 (0 Points) Suppose that the processor is executing a program that is running at the speed of the main memory; i.e., its progress is indicated by the amount of memory that it has accessed. The main memory is a 100 MHz 5-5-5-5 DRAM that accesses memory in 64-bit quantities. The notation 5-5-5-5 here means that it takes 5 memory cycles to read 64 bits (8 bytes) from memory, and each consecutive 8 bytes requires another 5 memory cycles....
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hw2 - CSE 422S (Fall 2009) Operating Systems Organization...

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