# compArch - Computer Architecture(CSE 422S Dante Cannarozzi...

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Computer Architecture (CSE 422S) Dante Cannarozzi Washington University in St. Louis [email protected] www.cse.wustl.edu/~djc2

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2 -Ken Wong, Jan 2008 Assessment 0 5 10 15 20 25 30 35 40 45 50 3 points* 2 points 1 point 0 points
3 -Ken Wong, Jan 2008 Topics Instruction execution » Registers » Pipelining CPU-Memory speed gap Cache memory » Temporal locality » Cache complexities (cache line-size, latency) Virtual memory Simple interrupts System call

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4 -Ken Wong, Jan 2008 Matrix Multiply Example C-Level Code: int A[N][N], B[N][N], C[N][N]; for (int i=0; i < N; i++) for (j=0; j < N; j++) { C[i][j] = 0; for (k=0; k < N; k++) { C[i][j] = C[i][j] + (A[i][k] * B[k][j]); } } Machine- Level: . . . Initialize pointers . . . L: if (inner loop done) Exit inner loop; R4 <-- *R1; // Load register 4 from memory R5 <-- *R2; // Load register 5 from memory R4 <-- R5 * R4; // Multiply R6 <-- R6 + R4; // Value of C[i][j] *R3 <-- R6; // Store result back to memory R1 = R1 + 4; // Move pointer to next A[][] R2 = R2 + … ; // Move pointer to next B[][] goto L; // End of inner loop A B C Addr of A[i][k] Addr of B[k][j]
5 -Ken Wong, Jan 2008 Hardware Context Instructions Heap Stack instruction I’ PC SP instruction I I IR SR GR[0] GR[7] Address of next instruction Current instruction Stack Pointer General Registers Status Register Processor Status Word low high Save/restore hdw context when switching from one process to another

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6 -Ken Wong, Jan 2008 Processor Registers Program Counter (PC) » Contains address of next instruction Instruction Register (IR) » Contains the most recently fetched instruction Status Register (SR) » Results of comparisons, errors, etc. » Sometimes called Processor Status Word (PSW)) Stack Pointer (SP) » Address of the top stack element General Registers (R[0]. .R[7]) » Operands
7 -Ken Wong, Jan 2008 250 MHz SRAM Pentium Clock Speeds CPU Registers L1 Cache Bridge Main Memory PCI Bus (32 or 64 bits), 33 MHz Controller Controller ... ... L2 Cache Disk Drives Network Video 100 MHz, 32-Bit Processor Bus 500 MHz Pentium 100 MHz SDRAM 2 nsec 10 nsec 4 nsec 30.3 nsec Need for asynchrony between components » Buffers smooth out traffic May still get “stalls”

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8 -Ken Wong, Jan 2008 Evolution of Intel Processor Features Processor Date Frequenc y Transistor s Caches Pentium 1993 60 MHz 3.1 M L1: 16KB Pentium Pro 1995 200 MHz 5.5 M L1: 16 KB L2: 256 KB Pentium II 1997 266 MHz 7 M L1: 32 KB L2: 256 KB Pentium III 1999 500 MHz 8.2 M L1: 32 KB L2: 512 KB Pentium 4 2000 1.5 GHz 42 M * L1: 8 KB * L2: 256 KB Xeon 2002 1.70 GHz 42 M * L1: 8 KB * L2: 512 KB Pentium M 2004 2.00 GHz 140 M * L1: 64 KB * L2: 2 MB * On-die caches 1 MHz = 10 6 cycles per sec, 1 GHz = 10 9
9 -Ken Wong, Jan 2008 Pipelining Concept Sequential Process Example (4 operations) » op(0); op(1); op(2); op(3);

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compArch - Computer Architecture(CSE 422S Dante Cannarozzi...

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