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3/29/09 8:31 PM
Mallard ECE 290: Computer Engineering I  Spring 2009  HWK #3 Solutions
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HWK #3 Solutions
Problem 3.1
a. To draw a 2level NAND network, we first need to write f in SOP form.
f(a,b,c,d) = (a + b') XOR (a' + c + d)
= (a + b')' (a' + c + d) + (a + b') (a' + c +
d)'
= a'b(a' + c + d) + (a + b')ac'd'
= a'b + ac'd'
b. To draw a 2level NOR network, we first need to write f in POS form.
f(a,b,c,d) = a'b + ac'd'
= (a' + c') (a' + d') (b + a) (b + c') (b +
d')
= (a' + c') (a' + d') (b + a)
Problem 3.2
a. The simplified SOP expressions for the outputs are:
w
= d
3
+
d
2
(d
1
'd
0
')'
= d
3
+
d
2
d
0
+
d
2
d
1
x
= d
0
'd
1
'd
2
+
d
2
'(d
1
'd
0
')'
=
d
2
d
1
'd
0
'
+ d
2
'd
0
+ d
2
'd
1
y
= d
1
d
0
+ d
1
'd
0
'
z
= d
0
'
b. The 2level NAND circuit is shown below.
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Mallard ECE 290: Computer Engineering I  Spring 2009  HWK #3 Solutions
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c. The circuit in part (b) has:
three 3input NAND gates
seven 2input NAND gates
four inverters to compute d
0
', d
1
', d
2
', and d
3
'.
The original circuit has:
eight 2input NAND gates
five inverters to compute (d
0
'd
1
'), d
0
', d
1
', d
2
', and d
3
'.
We have here a typical speed vs. cost (hardware) tradeoff.
The original circuit has fewer components and so would be cheaper to build.
The circuit in part (b) has 3 levels: 2 levels of NANDs plus 1 level of inverters. The original
circuit has 5 levels: 3 levels of NANDs plus 2 levels of inverters. So the circuit in part (b) would
compute the output more quickly.
d. We know that a NAND gate with inverted inputs is equivalent to an OR gate. From this, we can slide
the invertors on the intermediate NAND gates (NAND gates that have direct connection to the inputs)
to transform the gates near the output to OR gates. The OR gates can then be changed to NOR gates
by adding invertors in front of the OR gates and then complementing the output of the NOR gates.
We also know that an AND gate with inverted inputs is equivalent to a NOR gate. By using this fact,
we can transform the AND gates (they used to be NAND, but we have already moved the inverters in
the previous step) to NOR gates. We have to be careful when sliding invertors on connections that
branch to multiple locations (i.e. the output d
0
'd
1
', when sliding the inverters to the right, an extra
inverter is added to the two noncomplemented branches, while the third is canceled out). See the
circuit diagram below for the final result:
3/29/09 8:31 PM
Mallard ECE 290: Computer Engineering I  Spring 2009  HWK #3 Solutions
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This note was uploaded on 11/16/2009 for the course ECE 290 taught by Professor Brown during the Spring '08 term at University of Illinois at Urbana–Champaign.
 Spring '08
 BROWN

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