Mallard ECE 290_ Computer Engineering I - Spring 2009 - HWK #7 Solution

# Mallard ECE 290_ - Mallard ECE 290 Computer Engineering I Spring 2009 HWK#7 Solution 8:31 PM HWK#7 Solution ECE 290 Problem 7.1 Problem Set#7 Due

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3/29/09 8:31 PM Mallard ECE 290: Computer Engineering I - Spring 2009 - HWK #7 Solution Page 1 of 6 HWK #7 Solution ECE 290 Problem Set #7 Due: March 11, 2009 Problem 7.1.

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3/29/09 8:31 PM Mallard ECE 290: Computer Engineering I - Spring 2009 - HWK #7 Solution Page 2 of 6 Problem 7.2. (a) C D Q+ (i) Q+ = (Qbar (CD)')' = (Q (CD')')'' + CD = CD + QC' + QD = CD + C'Q .
3/29/09 8:31 PM Mallard ECE 290: Computer Engineering I - Spring 2009 - HWK #7 Solution Page 3 of 6 https://mallard.cites.uiuc.edu/ECE290/material.cgi?SessionID=ramait…efault&title=HWK%20%237%20Solution&bodyargs=&id=hwk07_s09_soln&num= 0 0 Q 0 1 Q 1 0 0 1 1 1 (ii) This circuit has D and D' feeding into the NAND gates, so this corresponds to having S and R never equal. (b) (i) (ii) C D w x y z 0 0 1 1 y z 0 1 1 1 y z 1 0 1 0 0 1 1 1 0 1 1 0 (iii) Yes, the circuit drawn is a D latch. C is the control input and y is the state. When C = 0, then w = x = 1 and the state y persists. When C = 1: if D = 0 then w = 1 and x = 0 and the next state is y+ = 0. When C = 1: If D = 1 then w = 0 and x = 1 and the next state is y+ = 1. Problem 7.3 Consider the outputs of the D latch to be Y and Y'. When C = 0, the D latch is enabled and the Y and Y' are sensitive to changes in the D input where Y = D. With C = 0, the SR latch is disabled, so outputs Q and Q' are steady. When the clock goes from 0 to 1, the D latch becomes disabled after a short delay from the inverter,

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## This note was uploaded on 11/16/2009 for the course ECE 290 taught by Professor Brown during the Spring '08 term at University of Illinois at Urbana–Champaign.

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Mallard ECE 290_ - Mallard ECE 290 Computer Engineering I Spring 2009 HWK#7 Solution 8:31 PM HWK#7 Solution ECE 290 Problem 7.1 Problem Set#7 Due

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