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Unformatted text preview: IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005 1265 A 2.4-GHz RF Sampling Receiver Front-End in 0.18- " m CMOS Darius Jakonis, Kalle Folkesson, Jerzy D˛abrowski, Patrik Eriksson , Member, IEEE , and Christer Svensson , Fellow, IEEE Abstract— This paper presents an integrable RF sampling re- ceiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applica- tions in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18- m CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconver- sion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an ss Q of C 5.5 dBm, a gain of 1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip con- sumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm P . Index Terms— Bandpass filters, CMOS analog integrated cir- cuits, mixers, radio receivers, sample and hold circuits, switched- capacitor filters. I. INTRODUCTION T HE rapid growth of wireless communications and the emergence of new standards increases the demand for low cost multimode radio receivers. For portable battery-powered receivers, a high level of integration, high flexibility, and low power dissipation are essential issues [1]. One approach to achieve multimode operation in a receiver is to design hard- ware, which can be reconfigured by software. This approach is known as software-defined radio [2]. In transition from traditional radio architectures to soft- ware-defined radio, most signal processing is shifted from the analog to the digital domain. This imposes more stringent performance requirements on the analog-to-digital (A/D) con- version, where a high dynamic range must be combined with a high sampling rate [3]. A too “tough” requirement on dynamic range leads to excessive power consumption, inhibiting the use of software-defined radio in portable receivers [4]. To relax the requirements for high dynamic range and high sampling rate, discrete-time signal processing can be employed prior to the A/D converter. Switched-capacitor (SC) circuits are often used Manuscript received May 11, 2004; revised February 16, 2004. This work was supported by Intel Corporation and the STRINGENT program....
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This note was uploaded on 11/17/2009 for the course ET 1 taught by Professor Gounot during the Spring '09 term at École Normale Supérieure.

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