class6-wrapup - CS:APP Chapter 4 Computer Architecture...

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Randal E. Bryant Carnegie Mellon University CS:APP CS:APP Chapter 4 CS:APP Chapter 4 Computer Architecture Computer Architecture Wrap-Up Wrap-Up http://csapp.cs.cmu.edu
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– 2 – CS:APP Overview Wrap-Up of PIPE Design Wrap-Up of PIPE Design Performance analysis Fetch stage design Exceptional conditions Modern High-Performance Processors Modern High-Performance Processors Out-of-order execution
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– 3 – CS:APP Performance Metrics Clock rate Clock rate Measured in Megahertz or Gigahertz Function of stage partitioning and circuit design Keep amount of work per stage small Rate at which instructions executed Rate at which instructions executed CPI: cycles per instruction On average, how many clock cycles does each instruction require? Function of pipeline design and benchmark programs E.g., how frequently are branches mispredicted?
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– 4 – CS:APP CPI for PIPE CPI CPI 1.0 1.0 Fetch instruction each clock cycle Effectively process new instruction almost every cycle Although each individual instruction has latency of 5 cycles CPI CPI > 1.0 1.0 Sometimes must stall or cancel branches Computing CPI Computing CPI C clock cycles I instructions executed to completion B bubbles injected (C = I + B) CPI = C/I = (I+B)/I = 1.0 + B/I CPI = C/I = (I+B)/I = 1.0 + B/I Factor B/I represents average penalty due to bubbles
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– 5 – CS:APP CPI for PIPE (Cont.) B/I = LP + MP + RP B/I = LP + MP + RP LP: Penalty due to load/use hazard stalling Fraction of instructions that are loads 0.25 Fraction of load instructions requiring stall 0.20 Number of bubbles injected each time 1 LP = 0.25 * 0.20 * 1 = 0.05 LP = 0.25 * 0.20 * 1 = 0.05 MP: Penalty due to mispredicted branches Fraction of instructions that are cond. jumps 0.20 Fraction of cond. jumps mispredicted 0.40 Number of bubbles injected each time 2 MP = 0.20 * 0.40 * 2 = 0.16 MP = 0.20 * 0.40 * 2 = 0.16 RP: Penalty due to ret instructions Fraction of instructions that are returns 0.02 Number of bubbles injected each time 3 RP = 0.02 * 3 = 0.06 RP = 0.02 * 3 = 0.06 Net effect of penalties 0.05 + 0.16 + 0.06 = 0.27 Typical Values
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– 6 – CS:APP Fetch Logic Revisited During Fetch Cycle During Fetch Cycle 1. Select PC 2. Read bytes from instruction memory 3. Examine icode to determine instruction length 4. Increment PC Timing Timing Steps 2 & 4 require significant amount of time F D rB M_ icode Pred ict PC va lC lP ifun rA Instruction memory increment predPC Need reg ids Instr lid A lign Sp lit Bytes 1-5 Byte 0 Se lect M_Bch M_va lA W_ W_va lM
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– 7 – CS:APP Standard Fetch Timing Must Perform Everything in Sequence Can’t compute incremented PC until know how much to increment it by Select PC Mem. Read Increment need_regids, need_valC 1 clock cycle
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– 8 – CS:APP A Fast PC Increment Circuit 3-bit adder need_ValC need_regids 0 29-bit incre- menter MUX High-order 29 bits Low-order 3 bits High-order 29 bits Low-order 3 bits 0 1 PC incrPC Slow Fast carry
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– 9 – CS:APP Modified Fetch Timing 29-Bit Incrementer 29-Bit Incrementer
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This note was uploaded on 11/17/2009 for the course CS:APP 422 taught by Professor Randale.bryantanddavidr.o'hallaron during the Spring '02 term at Carnegie Mellon.

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class6-wrapup - CS:APP Chapter 4 Computer Architecture...

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