class20 - 15-213 The course that gives CMU its Zip!...

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P6/Linux Memory System Oct. 31, 2002 Topics Topics P6 address translation Linux memory management Linux page fault handling memory mapping class20.ppt 15-213 “The course that gives CMU its Zip!”
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– 2 – 15-213, F’02 Intel P6 Internal Designation for Successor to Pentium Internal Designation for Successor to Pentium Which had internal designation P5 Fundamentally Different from Pentium Fundamentally Different from Pentium Out-of-order, superscalar operation Designed to handle server applications Requires high performance memory system Resulting Processors Resulting Processors PentiumPro (1996) Pentium II (1997) Incorporated MMX instructions » special instructions for parallel processing L2 cache on same chip Pentium III (1999) Incorporated Streaming SIMD Extensions » More instructions for parallel processing
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– 3 – 15-213, F’02 P6 Memory System bus interface unit DRAM external system bus (e.g. PCI) instruction fetch unit L1 i-cache L2 cache cache bus L1 d-cache inst TLB data TLB processor package 32 bit address space 32 bit address space 4 KB page size 4 KB page size L1, L2, and TLBs 4-way set associative inst TLB inst TLB 32 entries 8 sets data TLB 64 entries 16 sets L1 i-cache and d-cache 16 KB 32 B line size 128 sets L2 cache cache unified 128 KB -- 2 MB
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– 4 – 15-213, F’02 Review of Abbreviations Symbols: Symbols: Components of the virtual address (VA) TLBI: TLB index TLBT: TLB tag VPO: virtual page offset VPN: virtual page number Components of the physical address (PA) PPO: physical page offset (same as VPO) PPN: physical page number CO: byte offset within cache line CI: cache index CT: cache tag
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– 5 – 15-213, F’02 Overview of P6 Address Translation CPU VPN VPO 20 12 TLBT TLBI 4 16 virtual address (VA) ... TLB (16 sets, 4 entries/set) VPN1 VPN2 10 10 PDE PTE PDBR PPN PPO 20 12 Page tables TLB miss TLB hit physical address (PA) result 32 ... CT CO 20 5 CI 7 L2 and DRAM L1 (128 sets, 4 lines/set) L1 hit L1 miss
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– 6 – 15-213, F’02 P6 2-level Page Table Structure Page directory 1024 4-byte page directory entries (PDEs) that point to page tables one page directory per process. page directory must be in memory when its process is running always pointed to by PDBR Page tables: Page tables: 1024 4-byte page table entries (PTEs) that point to pages. page tables can be paged in and out. page directory ... Up to 1024 page tables 1024 PTEs 1024 PTEs 1024 PTEs ... 1024 PDEs
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– 7 – 15-213, F’02 P6 Page Directory Entry (PDE) Page table physical base addr Avail G PS A CD WT U/S R/W P=1 Page table physical base address : 20 most significant bits of physical page table address (forces page tables to be 4KB aligned) Avail : These bits available for system programmers G : global page (don’t evict from TLB on task switch) PS : page size 4K (0) or 4M (1) A : accessed (set by MMU on reads and writes, cleared by software) CD : cache disabled (1) or enabled (0) WT : write-through or write-back cache policy for this page table U/S
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This note was uploaded on 11/17/2009 for the course CS:APP 422 taught by Professor Randale.bryantanddavidr.o'hallaron during the Spring '02 term at Carnegie Mellon.

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class20 - 15-213 The course that gives CMU its Zip!...

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