05_DC_Transfer_Characteristics

05_DC_Transfer_Characteristics - Unit 5: DC Transfer...

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P.1 S.J.Chang NCKU/EE Unit 5: DC Transfer Characteristics ± Preface ± In unit 4, we have examined detail characteristics ( I - V and C - V ) and introduced their corresponding models of MOS transistors ± In this unit, we will calculate the DC transfer characteristics of logic gates using the transistors models. ± (Textbook) 2.5, 2.6 ± Outline ± DC transfer characteristics ± Switch-level RC delay models
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P.2 S.J.Chang NCKU/EE DC Transfer Characteristics ± Current depends on region of transistor behavior ± For what V in and V out are nMOS and pMOS in ± Cutoff? ± Linear? ± Saturation? V DD V in V out I dsp I dsn ± DC Response: V out vs. V in for a gate ± Ex: Inverter ± When V in = 0 V out = V DD ± When V in = V DD V out = 0 ± In between, V out depends on transistor size and current ± By KCL, must settle such that I dsn = | I dsp | ± We could solve equations but graphical solution gives more insight
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P.3 S.J.Chang NCKU/EE nMOS Operation ± V gsn = V in ± V dsn = V out Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V in < V tn V in > V tn V in > V tn V dsn < V gsn V tn V dsn > V gsn V tn V out < V in V tn V out > V in V tn V DD V in V out I dsp I dsn
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P.4 S.J.Chang NCKU/EE pMOS Operation ± V tp < 0 ± V gsp = V in –V DD ± V dsp = V out DD Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V in > V DD + V tp V in < V DD + V tp V in < V DD + V tp V dsp > V gsp V tp V dsp < V gsp V tp V out > V in V tp V out < V in V tp V DD V in V out I dsp I dsn
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P.5 S.J.Chang NCKU/EE I-V Characteristics ± Suppose pMOS is made wider than nMOS such that β n = p V gsn 1 V gsn 2 V gsn 3 V gsn 4 V gsn 5 V gsp 5 V gsp 4 V gsp 3 V gsp 2 V gsp 1 0V DD –V DD I dsn I dsp V dsn V dsp
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P.6 S.J.Chang NCKU/EE Load Line Analysis (1/2) ± Current vs. V out , V in ± For a given V in : ± Plot I dsn , I dsp vs. V out ± V out must be where I dsn = | I dsp | 0V DD I dsn , | I dsp | V out V in 1 V in 2 V in 3 V in 4 V in 5 V in 4 V in 3 V in 2 V in 1 V in 0 Note: V gsn = V in V gsp = V in –V DD V dsn = V out V dsp = V out V DD
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P.7 S.J.Chang NCKU/EE Load Line Analysis (2/2) 0 V DD I dsn , | I dsp | V out ± Vin = 0 V in = 0.2V DD = 0.4V = 0.6V = 0.8V = V DD Load line summary V in 0 V in 1 V in 1 V in 2 V in 2 V in 3 V in 3 V in 4 V in 4 V in 5
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P.8 S.J.Chang NCKU/EE DC Transfer Curve of CMOS Inverter ± Transcribe points onto V in vs. V out plot ± Logic gate switching threshold voltage ±
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This note was uploaded on 11/26/2009 for the course ELECTRICAL AVLSI taught by Professor Son-yicheng during the Spring '09 term at UFF.

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05_DC_Transfer_Characteristics - Unit 5: DC Transfer...

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