# chapter4 - CSCI-365 Computer Organization Lecture Chapter 4...

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CSCI-365 Computer Organization Lecture Note : Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson & Hennessy, ©2005 Some slides and/or pictures in the following are adapted from: slides ©2008 UCB Chapter 4

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Truth Tables Uniquely Define CL Function
Truth Table A truth table defines the outputs of a logic block for each set of inputs E.g., Consider a block with 3 inputs A, B, C and an output E that is true only if exactly 2 inputs are true (DONE IN CLASS)

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Logic Gates
Logic Gates

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2-input gates extend to n-inputs N-input XOR is the only one which isn’t so obvious It’s simple: XOR is a 1 iff the # of 1s at its input is odd
Boolean Algebra George Boole, 19 th Century mathematician Developed a mathematical system (algebra) involving logic later known as “Boolean Algebra” Primitive functions: AND, OR and NOT The power of BA is there’s a one-to-one correspondence between circuits made up of AND, OR and NOT gates and equations in BA + means OR,• means AND, x means NOT

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Canonical Forms Sum of products
Laws of Boolean Algebra

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BA: Circuit & Algebraic Simplification BA also great for circuit verification Circ X = Circ Y? use BA to prove!
Canonical Forms

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Truth Table Gates (e.g., majority circ.) (DONE IN CLASS)
Common Logic Blocks - Multiplexor Multiplexor or selector: one of N inputs is reflected on the output depending on the value of the log 2 N selector bits. E.g., 2-input mux

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Takes in N inputs and activates one of 2 N outputs I 0 I 1 O 0 O 1 O 2 O 3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 2-to-4 Decoder I 0 O 0 Common Logic Blocks - Decoder I 1 O 1 O 2 O 3 2-4 Decoder (DONE IN CLASS)
Arithmetic and Logic Unit Most processors contain a special logic block called “Arithmetic and Logic Unit” (ALU)

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Arithmetic and Logic Unit A common way to implement the ALU is to provide a CL block for each of the possible ALU functions The inputs, A and B, get distributed to all the blocks The output of the proper block is selected with a mux Every function of the ALU is computed internally to the ALU on every cycle, but only one of the results is sent to the output
Arithmetic and Logic Unit The logical operations as defined by the MIPS ISA are bitwise operations – In the case of AND, the resultant bit r i is generated as a i AND b i . The circuit to perform this operation is simply a collection of 32 AND gates Similarly, the OR block is a collection of 32 OR gates The add/subtract block is significantly more complex

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Adder/Subtracter Design -- how? Truth-table, then determine canonical form, then minimize and implement as we’ve seen before This technique is only effective for very narrow adders, truth table too large for wider adders Look at breaking the problem down into smaller pieces that we can cascade or hierarchically layer We will design the smaller pieces individually, then wire them together to create entire wide adder

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Multiplexor selects between ADD, OR, AND operations 1-Bit ALU with ADD, OR, AND
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## This note was uploaded on 11/26/2009 for the course MATH AND C CSCI365 taught by Professor Laurencetianruoyang during the Spring '09 term at St. Francis Xavier, Antigonish.

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chapter4 - CSCI-365 Computer Organization Lecture Chapter 4...

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