lec_09_pipelining_2_spr08_s

lec_09_pipelining_2_spr08_s - Lecture 9 Pipelining...

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EE-449 Lec. 09 of 32 Lecture 9 – Pipelining EE-449 Computer Organization Spring 2008 Salvador Fallorina CSULA Pipelined Datapath & Control 04-28-08 1 Fallorina | CSULA
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EE-449 Lec. 09 of 32 Review: Pipeline Capabilities Pipelining takes advantage of parallelism by overlapping execution  of multiple instructions Pipelining can work since each execution step uses a different  functional unit, idle resources can be used by other instructions Pipelining doesn’t speedup execution of a single instruction, it  increases  throughput  of entire program. Entire programs run faster. Fallorina | CSULA 2
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EE-449 Lec. 09 of 32 Review: Pipelined Performance In the best case, a 5-stage pipeline will be  executing 5 instructions at a time. One  instruction will be finished on every cycle! Fallorina | CSULA 3 CPI Clock Cycle Time Single-cycle 1 high Multicycle                    >1 low Pipelined ~1 low
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EE-449 Lec. 09 of 32 Review: Pipelining Fallorina | CSULA 4 Pipeline Depth  = Number of pipeline stages = 5 At full pipeline, CPI =1 Sequence of instructions Short clock cycle time Time in clock cycles
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of 32 Review: Limits to Speedup Instructions forced to have need same number of stages to avoid  resource conflicts.  5 lw R-type sw
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EE-449 Lec. 09 of 32 Pipeline Hazards Hazards may prevent next instruction from executing  during its designated clock cycle (Resulting in undesired  pipeline stalls and “bubbles”) Structural Hazards Conflicts for resources at the same clock cycle These may be avoided through adding more functional units Data Hazards Instructions may depend on result of previous instruction still in the pipeline These may be avoided through “forwarding” etc.
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This note was uploaded on 11/27/2009 for the course EE 454 taught by Professor Puvvada during the Fall '08 term at USC.

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lec_09_pipelining_2_spr08_s - Lecture 9 Pipelining...

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