lec_08_pipelining_1_spr08_s

lec_08_pipelining_1_spr08_s - Lecture 8 Datapath &...

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EE-449 Lec. 08 of 43 Lecture 8 – Datapath & Control - Pipelining EE-449 Computer Organization Spring 2008 Salvador Fallorina CSULA 04-21-08 1 Fallorina | CSULA
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EE-449 Lec. 08 of 43 Example: ori instruction Problem:  Build multicycle datapath and control just for the  instruction  ori Represent control as both FSM and microprogram;  implement FSM with a PLA and state elements. Notes: It’s essentially a 1-instruction processor (that still goes  through the instruction fetch and decode stages) Only include the necessary datapath elements and  control signals Fallorina | CSULA 2
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EE-449 Lec. 08 of 43 ori Instruction Start with: Syntax    ori rt, rs, Imm RTL          R[rt] = R[rs]| zeroExtendImm Instruction format Fallorina | CSULA 3 6 5 5 16 opcode rs rt immediate I 31 26 25 21 20 16 15 0
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EE-449 Lec. 08 of 43 ori Datapath Fallorina | CSULA 4 ori rt, rs, Imm R[rt] = R[rs]| zeroExtendImm
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EE-449 Lec. 08 of 43 ori Control: FSM Fallorina | CSULA 5 Fetch instruction from memory and place in IR Set PC = PC + 4 Calc A | zeroExtendImm Write back result to register Instruction decode Note: we can also merge state 1 and 2 into a single state
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EE-449 Lec. 08 of 43 ori : FSM Implementation Fallorina | CSULA 6 Output Equations (= states where output is asserted) MemRead = state0 = S1·S0 ALUSrcA = state2 = S1·S0 ALUSrcB = state2 ALUOp1 = state2 ALUOp0 = state2 PCWrite = state0 RegWrite = state3 = S1·S0 IRWrite = state0 + MemWrite = 0 (just connect to gnd) Next State Equations NextState0 = state3 NextState1 = state0 NextState2 = state1·ori NextState3 = state2 NS1 NS0 NextState0 0 0 NextState1 0 1 NextState2 1 0 NextState3 1 1 Next State Bits (2 bits to represent 4 states) NS1 = NextState2 + NextState3 = state1·ori +state2 NS0 = NextState1 + NextState3 = state0 + state2
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EE-449 Lec. 08 of 43 ori : FSM Implementation into PLA Fallorina | CSULA 7
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EE-449 Lec. 08 of 43 ori : FSM Implementation into PLA Fallorina | CSULA 8
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EE-449 Lec. 08 of 43 ori : FSM Implementation into PLA Fallorina | CSULA 9
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EE-449 Lec. 08 of 43 PLA example 1 Fallorina | CSULA 10 Inputs Outputs x 2 x 1 x 0 y 1 y 0 1 y 1 = x 2 ·x 1 ·x 0 + x 2 ·x 1 ·x 0 + x 2 ·x 1 ·x 0 y 0 = x 2 ·x 1 ·x 0 + x 2 ·x 1 ·x 0 1. Given truth table 2. Derive output equations in terms of minterms (i.e. sum-of-products form): 3. Draw logic diagram for each product term A shortcut notation is shown below x 2 ·x 1 ·x 0 x 2 ·x 1 ·x 0 x 2 ·x 1 ·x 0 x 2 ·x 1 ·x 0
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EE-449 Lec. 08 of 43 PLA example 1 Fallorina | CSULA 11 4. Add the product terms to get the outputs. 5. In simpler notation, leaving out the AND & OR gates x 2 x 1 x 0 x 2 x 1 x 0 y 1 y 0 y 1 y 0 Inputs Outputs y 1 = x 2 ·x 1 ·x 0 + x 2 ·x 1 ·x 0 + x 2 ·x 1 ·x 0 y 0 = x 2 ·x 1 ·x 0 + x 2 ·x 1 ·x 0 where
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EE-449 Lec. 08 of 43 PLA example 2 Fallorina | CSULA 12
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EE-449 Lec. 08 of 43 Review: Exception Handling Fallorina | CSULA 13 Detect overflow  by connecting  overflow signal  to controller Transfer  control to OS  through  specified  address -Storage of  instruction - Storage  of cause (0: undefined  instr; 1:  overflow)
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lec_08_pipelining_1_spr08_s - Lecture 8 Datapath &...

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