lec_03_datapath_and_control_spr08s

lec_03_datapath_and_control_spr08s - Lecture 3 Datapath and...

Info icon This preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
  EE-449 Lec. 03   of 41 Lecture 3 – Datapath and Control (Single-Cycle) EE-449 Computer Organization Spring 2008 Salvador Fallorina CSULA 1 04-02-08
Image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
  EE-449 Lec. 03   of 41 Computer Organization Level 2 S. Fallorina | CSULA Applications (Office, Photoshop, games, …) Operating System (Windows, Unix, Linux…) Instruction Set Architecture (ISA) (MIPS, x86) Microarchitecture Digital Logic (gates, flip-flops, PLAs, …) Circuits Physical CPU Memory Input/ Output Datapath Control Software Hardware Microarchitecture: implementation of the ISA
Image of page 2
  EE-449 Lec. 03   of 41 Objective To design and build a CPU that  implements a subset of the MIPS ISA Data transfer: lw, sw Arithmetic-logical: add (and other R-types) Branch: beq Jump: j  S. Fallorina | CSULA 3
Image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
  EE-449 Lec. 03   of 41 The CPU: An Abstract View S. Fallorina | CSULA 4 Datapath: describes the pathways and hardware where the instructions and data flow during execution Control: determines the how the data and instructions flow and how the hardware is used Registers Register # Data Register # Data memory Address Data Register # PC Instruction ALU Instruction memory Address Controller add $t0,$t1,$t2 START RESULT R[rd]=R[rs]+R[rt]
Image of page 4
  EE-449 Lec. 03   of 41 Building the Single-Cycle Datapath S. Fallorina | CSULA 5 Registers Register # Data Register # Data memory Address Data Register # PC Instruction ALU Instruction memory Address add $t0,$t1,$t2 START RESULT R[rd]=R[rs]+R[rt] Approach: Divide datapath into stages Benefit: More manageable and easier to understand Smaller stages are easier to design and optimize Provides framework for multicycle datapath and pipelining IF ID EXE MEM WB Datapath or Execution Process
Image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
  EE-449 Lec. 03   of 41 The Five Datapath Stages S. Fallorina | CSULA 6 IF ID EX MEM WB Instruction Fetch Instruction Decode & Register Fetch Execution Memory Access Write Back Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Single-Cycle Datapath: execution takes one clock cycle per instruction Multicycle Datapath: execution takes one clock cycle per stage Clock Cycle:
Image of page 6
  EE-449 Lec. 03   of 41 Steps in Building the Datapath & Control 1. Study the ISA.  Determine  specifications and  requirements ISA details: # of bits, instruction format, register set, etc. Express the operation of each instruction in a Register  Transfer Language (RTL) 1. Build the datapath.  For each instruction, go through  each stage and determine: Datapath components and interconnections that implement the  RTL Control signals (also depends on single-cycle and multicycle approaches) 1. Design the controller  that generates the appropriate  control signals at the correct time.
Image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern