lec_03_datapath_and_control_spr08s

lec_03_datapath_and_control_spr08s - Lecture 3 Datapath and...

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  EE-449 Lec. 03   of 41 Lecture 3 – Datapath and Control (Single-Cycle) EE-449 Computer Organization Spring 2008 Salvador Fallorina CSULA 1 04-02-08
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  EE-449 Lec. 03   of 41 Computer Organization Level 2 S. Fallorina | CSULA Applications (Office, Photoshop, games, …) Operating System (Windows, Unix, Linux…) Instruction Set Architecture (ISA) (MIPS, x86) Microarchitecture Digital Logic (gates, flip-flops, PLAs, …) Circuits Physical CPU Memory Input/ Output Datapath Control Software Hardware Microarchitecture: implementation of the ISA
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  EE-449 Lec. 03   of 41 Objective To design and build a CPU that  implements a subset of the MIPS ISA Data transfer: lw, sw Arithmetic-logical: add (and other R-types) Branch: beq Jump: j  S. Fallorina | CSULA 3
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  EE-449 Lec. 03   of 41 The CPU: An Abstract View S. Fallorina | CSULA 4 Datapath: describes the pathways and hardware where the instructions and data flow during execution Control: determines the how the data and instructions flow and how the hardware is used Registers Register # Data Register # Data memory Address Data Register # PC Instruction ALU Instruction memory Address Controller add $t0,$t1,$t2 START RESULT R[rd]=R[rs]+R[rt]
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  EE-449 Lec. 03   of 41 Building the Single-Cycle Datapath S. Fallorina | CSULA 5 Registers Register # Data Register # Data memory Address Data Register # PC Instruction ALU Instruction memory Address add $t0,$t1,$t2 START RESULT R[rd]=R[rs]+R[rt] Approach: Divide datapath into stages Benefit: More manageable and easier to understand Smaller stages are easier to design and optimize Provides framework for multicycle datapath and pipelining IF ID EXE MEM WB Datapath or Execution Process
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  EE-449 Lec. 03   of 41 The Five Datapath Stages S. Fallorina | CSULA 6 IF ID EX MEM WB Instruction Fetch Instruction Register Fetch Execution Memory Access Write Back Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Single-Cycle Datapath: execution takes one clock cycle per instruction Multicycle Datapath: execution takes one clock cycle per stage Clock Cycle:
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EE-449 Lec. 03   of 41 1. Study the ISA.  Determine  specifications and  requirements ISA details: # of bits, instruction format, register set, etc. Express the operation of each instruction in a Register  Transfer Language (RTL) 1. Build the datapath.  For each instruction, go through  each stage and determine: Datapath components and interconnections that implement the  RTL Control signals (also depends on single-cycle and multicycle approaches) 1. Design the controller  that generates the appropriate  control signals at the correct time. S. Fallorina | CSULA
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This note was uploaded on 11/27/2009 for the course EE 454L at USC.

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lec_03_datapath_and_control_spr08s - Lecture 3 Datapath and...

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