lec_12_pipelining-memory_spr08_s

lec_12_pipelining-memory_spr08_s - EE-449 Lec. 12of...

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Unformatted text preview: EE-449 Lec. 12of 57Lecture 12 Pipelining and Memory HierarchyEE-449 Computer Organization Spring 2008Salvador FallorinaCSULA05-19-081Fallorina | CSULAEE-449 Lec. 12of 57Review: Pipeline HazardsFallorina | CSULA2HazardApproachStructural Hazards Stall Add hardwareData Hazards(arithmetic & loads) Stall Forwarding Stall & ForwardControl Hazards(beq) Stall Delayed Branches Branch PredictionEE-449 Lec. 12of 57Review: ForwardingForwarding data (by bypassing the register file)Fallorina | CSULA3EE-449 Lec. 12of 57Review: Datapath with Forwarding UnitFallorina | CSULA4EE-449 Lec. 12of 57Detecting Data Hazards with HardwareAn EX/MEM hazard occurs between the instruction currently in its EX stage and the previous instruction if:1. The previous instruction is going write to the register file (but not $0), and2. The destination register matches one of the ALU input/source registers in the EX stage.Or in equation form:if (EX/MEM.RegWriteand (EX/MEM.RegisterRd != 0)and (EX/MEM.RegisterRd == ID/EX.RegisterRs)) then ForwardA = 10if (EX/MEM.RegWriteand (EX/MEM.RegisterRd != 0)and (EX/MEM.RegisterRd == ID/EX.RegisterRt)) then ForwardB = 10Fallorina | CSULA5EE-449 Lec. 12of 57Detecting Data Hazards with HardwareAn MEM/WB hazard may occur between an instruction in the EX stage and the instruction from 2 cycles before:1. The previous instruction (2 cycles before) is going write to the register file (but not $0), and2. The destination register matches one of the ALU input/source registers in the EX stage.Or in equation form:if (MEM/WB.RegWriteand (MEM/WB.RegisterRd != 0)and (EX/MEM.RegisterRd != ID/EX.RegisterRs) and (MEM/WB.RegisterRd == ID/EX.RegisterRs)) then ForwardA = 01if (MEM/WB.RegWriteand (MEM/WB.RegisterRd != 0) and (EX/MEM.RegisterRd != ID/EX.RegisterRs) and (MEM/WB.RegisterRd == ID/EX.RegisterRt)) then ForwardB = 01Fallorina | CSULA6EE-449 Lec. 12of 57Ex. Stall for one cycle and forwardReview: Stall & ForwardFallorina | CSULA7EE-449 Lec. 12of 57Hazard Unit: Detects Load-Use Hazard & StallsFallorina | CSULA8EE-449 Lec. 12of 57Review: Load-Use Hazard DetectionDetection:A hazard occurs if:1.The previous instruction was lw, and2.The lw destination is one of the current source registersExpressed in equations:if (ID/EX.MemRead == 1and (ID/EX.RegisterRt == Rsor ID/EX.RegisterRt == Rt))then Fallorina | CSULA9EE-449 Lec. 12of 57Review: Implementing StallsStalls can be implemented by preventing the next two instructions from continuing. (Instruction stays in the same state for a cycle. )This can be done by:Preventing the IF/ID register from being written in the ID stage. (Add IF/IDWrite control) Setting IF/IDWrite=0 keeps same instruction in ID stage...
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lec_12_pipelining-memory_spr08_s - EE-449 Lec. 12of...

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