On the block diagram use a shift register with three

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Unformatted text preview: each wired to one LED indicator. You can use a Wait function to slow down the action for demonstration. Note that the While Loop control is left unwired. Each time this VI is called, the next value is returned. On the front panel, select the three outputs as connections in the icon editor and save this program as a subVI called Rotate.vi. Figure 2-6. Rotate.vi Front Panel and Block Diagram National Instruments Corporation 2-3 Fundamentals of Digital Electronics Lab 2 Encoders and Decoders Below is the truth table for the modulo 6 counter. Run the program seven times to observe the action. Table 2-2. Truth Table for Modulo 6 Counter Cycle 1 2 3 4 5 6 7 Q1 0 1 1 1 0 0 0 Q2 0 0 1 1 1 0 0 Q3 0 0 0 1 1 1 0 same as cycle 1 The output repeats after six counts, hence the name modulo 6 counter. Encoder There is no a priori reason to decide which output corresponds to which count. However, a little foresight makes the choices easier: Table 2-3. Digital Die Encoding Scheme # 6 4 2 1 3 5 Q1 0 1 1 1 0 0 Q2 0 0 1 1 1 0 Q3 0 0 0 1 1 1 Q1 1 0 0 0 1 1 Q2 1 1 0 0 0 1 Q3 1 1 1 0 0 0 For example, each output has three (1) states and three (0) states. One of these outputs, for example Q3, could signify odd states 1, 3, and 5. Another output state, for example Q2, can then signify the family 4, 5, 6. These two lines then decode two of the base patterns for "free." The two remaining base patterns are decoded with a particular pattern of the three counter lines. To this end, a three-input AND gate built in the last lab together with an inverter can be used. Not 1 (Base Pattern B) is decoded with the combination Q1 & Q2 & Q3, and the final base state "6" is decoded with Q1 & Q2 & Q3. Fundamentals of Digital Electronics 2-4 National Instruments Corporation Lab 2 Encoders and Decoders Figure 2-7. Encode.vi Front Panel and Block Diagram The encoder is built by placing three Boolean indicators on the front panel together with four LED indicators. The encoder is wired by translating the words of the above paragraph into a circuit. Virtual Dice (modulo 6) Counter stop Figure 2-8. Function Schematic for Digital Dice Encoder To roll the virtual die, a high-speed counter will cycle through the six states. These states are encoded on three output lines. In practice, the counter cycles until a stop command is issued to the counter. Whatever state the counter has on its output will be the roll value. A clock with a speed greater than 1 kHz ensures the randomness of the roll. An encoder VI converts the three counter lines into the four control lines for the base patterns. These in turn set the dots on the virtual die to the correct output code. It is now a simple case of assembling all the components--counter, encoder and display--into a VI called Dice.vi. Just as you would build electronic circuits by assembling gates, latches, switches, and displays, LabVIEW simulates this process by building complex functions from simpler ones. National Instruments Corporation 2-5 Fundamentals of Digital Electronics Lab 2 Encoders and Decoders Figure 2-9. Dice.vi Block Diagram. Note the Similarity with the Function Schematic Above Now, flip the front panel switch and let the good times roll! Lab 2 Library VIs (Listed in the Order Presented) Display.vi (LED displays for virtual die) Rotate.vi (modulo 6 counter) Encoder.vi (converts counter codes to display codes) 3 AND.vi (subVI used in Encoder.vi) Dice.vi (let the good times roll) Fundamentals of Digital Electronics 2-6 National Instruments Corporation Lab 3 Binary Addition Before proceeding with this lab, it is helpful to review some details of binary addition. Just as in decimal addition, adding 0 to any value leaves that number unchanged: 0 + 0 = 0, while 1 + 0 = 1. However, when you add 1 + 1 in binary addition, the result is not "2" (a symbol which does not exist in the binary number system), but "10"; a "1" in the "twos place" and a zero in the "ones place." If you write this addition vertically, you would recite, "One and one are two; write down the zero, carry the one": 1 +1 10 Figure 3-1. Single-Bit Addition Below is the truth table for single-bit addition. There are two input columns, one for each addend, A1 and A2, and two output columns, one for the ones-place sum and one for the carried bit: Table 3-1. Truth Table for Addition A1 + A2 0 0 1 1 0 1 0 1 = Sum with Carry 0 1 1 0 0 0 0 1 National Instruments Corporation 3-1 Fundamentals of Digital Electronics Lab 3 Binary Addition Which of the fundamental gates can you use to implement the output columns? Note that A1 XOR A2 reproduces the Sum output, and A1 AND A2 the Carry output, so a LabVIEW implementation of this 1-bit addition truth table is Figure 3-2. Half Adder Built from XOR and AND Gates This digital building block is called a "half adder." The term "half adder" refers to the fact that while this configuration can generate a signal to indicate a carry to the next highest order bit, it cannot accept a carry from a lower-order adder. A "...
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This note was uploaded on 12/01/2009 for the course S ss taught by Professor S during the Spring '09 term at Universidad Autonoma de Nuevo Leon - School of Business.

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