Q1 q2 q3 q4 d q d q d q d q q clock q q q figure

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Unformatted text preview: egister, D. Q1 Q2 Q3 Q4 D Q D Q D Q D Q Q Clock Q Q Q Figure 4-6. 4-Bit Ring Counter Using Integrated Circuit Chips In the above case, the outputs have been preset to [0110]. Load and run Rotate.vi. Observe how the outputs cycle from [0110] to [0011] to [1001] to [1100] and back to [0110]. It takes four clock cycles, hence this counter is a modulo 4 ring counter. In a special case where these four outputs are passed to the current drivers of a stepping motor, each change in output pattern results in the stepping motor advancing one step. A stepping motor with a 400-step resolution would then rotate 0.9 degrees each time the counter is called. A slight variation of the ring counter is the switched tail ring counter. In this case, the complement output Q of the last stage is fed back into the input. Modify Rotate.vi to make this change and save it as Switch Tail Ring Counter.vi. Fundamentals of Digital Electronics 4-4 National Instruments Corporation Lab 4 Memory: The D-Latch What is the modulus of the switch tail ring counter? Ring counters are often used in situations where events must be repeated at a uniform rate. Load and observe Billboard.vi, shown below, which simulates a light chaser. You can use the slide control to set the speed of the changing lights, and the 16 Boolean constants on the block diagram set the chase pattern. Lab 4 Library VIs (Listed in the Order Presented) D Latch.vi (LabVIEW simulation of a data latch) Shift.vi (4-bit shift register) Bucket.vi (8-bit shift register simulation) Rotate.vi (4-bit ring counter) Billboard.vi (16-bit ring counter used as a light chaser) National Instruments Corporation 4-5 Fundamentals of Digital Electronics Lab 4 Memory: The D-Latch Notes Fundamentals of Digital Electronics 4-6 National Instruments Corporation Lab 5 Pseudo-Random Number Generators In the last lab, simple ring counters were introduced as a means of building modulo-n counters. In this lab, feedback from a combination of advanced stages is combined and routed back into the input gate. If the correct combination is chosen, the output is of maximal length (that is, the modulus of the counter is 2N-1). For an 8-bit counter, N = 8 and (2N-1) = 255. These circuits, often called pseudo-random number generators (PRNG), have some interesting features. The sequences formed appear to be random over the short range, but in fact the sequence repeats after (2N-1) cycles. Furthermore, each pattern occurs only once during each sequence of (2N-1) numbers. Pseudo-random sequence and number generators have wide applications in computer security, cryptography, audio systems testing, bit error testing, and secure communications. A 6-Bit Pseudo-Random Number Generator In the following circuit, the outputs of the fifth and sixth D-latches have been exclusive NORed together to become the input to the shift register. It is assumed that initially, all outputs are zero. D 1 C Q D 2 C Q D 3 C Q D 4 C Q D 5 C Q D 6 C Q Clock Figure 5-1. 6-Bit PRNG Built from Six D-Latches and an XOR Gate National Instruments Corporation 5-1 Fundamentals of Digital Electronics Lab 5 Pseudo-Random Number Generators When Q5 and Q6 are 0, the output of the NXOR (see Lab 1) is 1. This HI value is loaded into the shift register at the input D1. On command from the clock, all bits shift to the right. The initial value of (000000) goes to (100000). It is easy to work through a few cycles to see the outputs Q1...Q6 follow the sequence: (000000) (100000) (110000) (111000) ---------After 63 cycles, the sequence returns to the initial state (000000). It is easy to simulate this circuit with a LabVIEW VI. Figure 5-2. LabVIEW VI to Simulate a 6-Bit PRNG A six-element shift register is placed on a While Loop. An exclusive OR gate and inverter are used for the NXOR gate whose inputs have been wired to Q5 and Q6. The loop index keeps track of the cycle count, and a delay of 500 ms allows the reader to observe the PRNG patterns. When running this VI, 6PRNG.vi, observe that cycles 0 and 63 are the same (that is, all bits are zero). An 8-Bit Pseudo-Random Sequencer An 8-bit PRNG uses the outputs Q4, Q5, Q6, and Q8 NXORed together to form the maximal length (2N-1) count sequence of 255. Fundamentals of Digital Electronics 5-2 National Instruments Corporation Lab 5 Pseudo-Random Number Generators Figure 5-3. LabVIEW Simulation of an 8-Bit PRNG As in the previous example, the parallel output can be observed on eight LED indicators. In addition, a pseudo-random sequence of ones and zeros is produced at Serial Out. Many digital circuits need to be tested with all combinations of ones and zeros. A "random" Boolean sequence of ones and zeros at [Serial Out] provides this feature. In this configuration, the circuit is called a pseudo-random bit sequencer, PRBS. On the front panel of the above VI, PRBS0.vi, you can view the Boolean sequence [Serial Out] on an LED indicator. Figure 5-4. Front Panel of the 8-Bit PRBS National Instruments Corporation 5-3 Fundamentals of Digital Electronics Lab 5 Pseudo-Random Number Generators A better way to view the bit sequence is as a bit trace. The Boolean bits are converted into a numeric value of...
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This note was uploaded on 12/01/2009 for the course S ss taught by Professor S during the Spring '09 term at Universidad Autonoma de Nuevo Leon - School of Business.

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