The system clock oversees the whole network of gates

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Unformatted text preview: ical CPU sequence, the program counter reaches out to the memory via the address bus to retrieve the next instruction. This instruction is passed over the data bus to the internal registers. The first part of the instruction is passed to the instruction decoder. It decides which data paths must be opened and closed to execute the instruction. In some cases, all the information needed to complete the operation is embedded within the instruction. An example of this type of instruction is "clear the accumulator." In other cases, the instruction needs additional information, and it returns to memory for the added data. An example of this type of instruction might be "load Register 2 with the data constant 5." Once all the information is in place, the instruction is executed by opening and closing various gates to allow execution of the instruction. Typical instructions available to all CPUs include simple instructions with data already inside the CPU, such as clear, complement, or increment the accumulator. More complex instructions use two internal registers or data coming from memory. This lab illustrates how the CPU executes simple and a few complex operations using basic logic functions. National Instruments Corporation 12-1 Fundamentals of Digital Electronics Lab 12 Central Processing Unit Operation of the Arithmetic and Logic Unit The arithmetic and logic unit (ALU) is a set of programmable two-input logic gates that operate on parallel bit data of width 4, 8, 16, or 32 bits. This lab will focus on 8-bit CPUs. The input registers will be called Register 1 and Register 2, and for simplicity the results of an operation will be placed in a third register called Output. The type of instruction (AND, OR, or XOR) is selected from the instruction mnemonic such as AND R1,R2. Figure 12-1. LabVIEW Simulation of an Arithmetic and Logic Unit In the LabVIEW simulation,, the registers R1 and R2 are represented by 1D arrays having Boolean controls for inputs. The output register is a Boolean array of indicators. The function (AND, OR, or XOR) is selected with the slide bar control. Data is entered into the input registers by clicking on the bar below each bit. Running the program executes the selected logic function. The following are some elementary CPU operations. What operation does or AND R1[$00], R2[$XX] OR R1[$FF], R2[$XX] XOR R1[$55], R2[$FF] represent? In each case, the data to be entered is included inside the [ ] brackets as a hexadecimal number such as $F3. Here, X is used to indicate any hexadecimal character. Investigate the above operations using The AND operation resets the output register to all zeroes, hence this operation is equivalent to CLEAR OUTPUT. The OR operation sets all bits high in the output register, hence this operation is equivalent to SET OUTPUT. The third operation inverts the bits in R1, hence this operation is equivalent to COMPLEMENT Register 1. Fundamentals of Digital Electronics 12-2 National Instruments Corporation Lab 12 Central Processing Unit Consider the operation "Load the Output Register with the contents contained in R1." In a text-based programming language, this operation might read "Output = Register 1." Set R1 in to some known value and execute the operation AND R1,R2[$FF]. Another interesting combination, XOR R1,R1, provides another common task, CLEAR R1. It should now be clear from these few examples that many CPU operations that have specific meaning within a software context are executed within the CPU using the basic gates introduced in Lab 1. The Accumulator In, CPU operations are executed by stripping off one bit at a time using the Index Array function, then executing the ALU operation on that bit. The result is passed on to the output array at the same index with Replace Array Element. After eight loops, each bit (0...7) has passed through the ALU, and the CPU operation is complete. Figure 12-2. LabVIEW VI to Simulate the Operation of an 8-Bit ALU In LabVIEW, it is not necessary to strip off each bit, as this task can be done automatically by disabling indexing at the For Loop tunnels. Array data paths are thick lines, but become thin lines for a single data path inside the loop. Study carefully the following example, which uses this LabVIEW feature. In many CPUs, the second input register, R2, is connected to the output register so that the output becomes the input for the next operation. This structure provides a much-simplified CPU structure, but more importantly, the output register automatically becomes an accumulator. National Instruments Corporation 12-3 Fundamentals of Digital Electronics Lab 12 Central Processing Unit Figure 12-3. ALU Simulation Uses the Auto Indexing at the For Loop Tunnels In, the previous accumulator value is input on the left, and the next accumulator value is output on the right. This programming style allows individual CPU instructions to be executed in sequence. Look at the following example, Load A with 5 then Com...
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