The transition of the comparator indicates this event

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Unformatted text preview: vi and observe the action. Note that as soon as the test level reaches the input level, the binary counter resets, and the ramp cycle starts all over again. In the display below, the input level was changed three times. Figure 8-4. Chart Display of the Ramp ADC in Operation An interesting feature, unique to the ramp ADC, is that the conversion time depends on the magnitude of the input signal. Small input levels are digitized faster than large input levels. The conversion time is thus dependent on the input signal magnitude and the clock circuitry speed. For an 8-bit DAC, variable conversion times may not be a problem when the clock is running at megahertz frequencies, but for 12-bit DACs, this property is a disadvantage. National Instruments Corporation 8-3 Fundamentals of Digital Electronics Lab 8 Analog-to-Digital Converters, Part I The ramp ADC works equally well with a down counter that runs from 255-0. The change of state of the comparator again signals the binary count that generates a test level equal to the input level. LabVIEW Challenge Design a ramp ADC that uses a down counter to generate the test waveform. Could you use an up/down counter to track the input level? Yes, such a conversion technique is called a tracking ADC, and it has the fastest conversion time. Tracking ADC The first task for the tracking ADC is to use some technique such as a ramp waveform to catch up to the input level. At that point, shown by the intersection of the ramp waveform with the input level, the tracking algorithm takes over. Figure 8-5. Tracking ADC Ramps Up to the Input Level Before Tracking Begins The tracking algorithm is simply, if test level is greater than the signal level, decrease the count by one else if test level is less than the signal level, increase the count by one and repeat forever. In the following example, a positive ramp ADC technique is used to initially catch up to the input level of 150.2. Once the input level is reached, the tracking algorithm takes over. Fundamentals of Digital Electronics 8-4 National Instruments Corporation Lab 8 Analog-to-Digital Converters, Part I By expanding the vertical scale, you can see the tracking algorithm in action. Figure 8-6. Tracking ADC Output when Input is Constant However, if the input level changes, the ADC must revert to a ramp waveform to catch up to the input level. Provided the clock is fast enough, the tracking can keep pace. But if the signal changes too quickly, the digitized signal is lost until the test level catches up again. In practice, it is the slewing speed of the DAC that limits the maximum input frequency that the tracking ADC can follow. Figure 8-7. A Sudden Change in the Input Level Causes the Test Level to Ramp Up to the New Level Because the tracking ADC uses an up/down counter, the algorithm has the same problem when the input signal suddenly falls below the test level. The tracking ADC reverts to a down ramp (Figure 8-8) until the test level reaches the input signal level. National Instruments Corporation 8-5 Fundamentals of Digital Electronics Lab 8 Analog-to-Digital Converters, Part I Figure 8-8. A Negative Change in the Input Level Causes the Test Level to Ramp Down to the New Level The VI called Tracking ADC.vi is used to demonstrate this technique and to generate all the above charts. The algorithm shown on the block diagram is quite simple. A LabVIEW Select function and the shift register on the While Loop implements the algorithm. Figure 8-9. LabVIEW VI for the Tracking ADC The Wait function is set to 0.10 second so that the user can observe the action on the front panel. You can also use the Operating tool to redefine the vertical axis scale to zoom in on the action as the simulation is in progress. To observe the tracker catching up to a varying input, reduce the input constant for the Wait function in Figure 8-9 to 1 ms. Lab 8 Library VIs (Listed in the Order Presented) Ramp.vi (8-bit ramp ADC, conversion slowed for easy viewing) Ramp4.vi (ramp ADC with no feedback from comparator) Ramp2.vi (8-bit ramp ADC with chart output) Tracking ADC1.vi Binary Counter.vi (subVI 8-bit binary counter) BIN_RST.vi (subVI 8-bit binary counter with external reset) DAC.vi (subVI 8-bit DAC) FlipFlop.vi (subVI) Fundamentals of Digital Electronics 8-6 National Instruments Corporation Lab 9 Analog-to-Digital Converters, Part II In the last lab, binary counters in the form of up and up/down counters were used to create test waveforms for ramp and tracking ADCs. Another popular ADC is based on a test waveform created from a successive approximation register (SAR). These ADCs are substantially faster than the ramp ADCs and have a constant and known conversion time. SARs make use of the binary weighting scheme by outputting each bit in succession from the most significant bit (MSB) to the least significant bit (LSB). The SAR algorithm is as follows: 1. Reset the SAR register and set the DAC to zero. 2. Set MSB of SAR: if VDAC is greater than Vin, then turn that bit off. else if...
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This note was uploaded on 12/01/2009 for the course S ss taught by Professor S during the Spring '09 term at Universidad Autonoma de Nuevo Leon - School of Business.

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