Unlike the d latch which has memory only until

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Unformatted text preview: mes along, the JK flip-flop has true memory. When the J and K inputs are low, the state of the outputs Q and Q are unchanged on clocking. Thus, information can be placed onto the output bit and held until requested at a future time. The output Q can be clocked low or high by setting the (J,K) inputs to (0,1) or (1,0), respectively. In fact, placing an inverter between J and K inputs results in a D-latch circuit. The schematic diagram for the JK flip-flop and its truth table is shown below. Note that the JK flip-flop can also be Set or Reset with direct logic inputs. Set J clk K Clr Q Q clock J 0 0 1 1 K 0 1 0 1 Q Q no change 0 1 1 0 Set Clr 0 0 1 1 0 1 0 1 Q Q disallowed 1 0 0 1 toggle clocked clocked logic direct logic Figure 6-1. JK Flip-Flop Logic Symbol and Truth Tables The first entry of the clocked truth table is the memory state, while the next two combinations are the latched states. What is new with the JK flip-flop is the fourth combination (1,1), which produces a toggle state. On clocking, the output changes from [1-->0] if 1 or [0-->1] if 0. This complement function is often referred to as bit toggling, and the resulting flip-flop (J and K inputs pulled HI) is called a T flip-flop. Because only one toggle occurs per output cycle, it takes two clock cycles to return the output state to its initial state. Load Binary1.vi and observe the operation of the T-flip-flop on clocking. National Instruments Corporation 6-1 Fundamentals of Digital Electronics Lab 6 JK Master-Slave Flip-Flop Figure 6-2. LabVIEW Simulation of a Divide-by-Two Counter Using a T Flip-Flop SubVI Each time the Run button is pressed, the clock changes state from HI-LO or LO-HI. How many times do you need to press the Run button to cycle the output bit from LO-HI-LO? It may be easier to make the correct observation by pressing the Run Continuously button. Because two clock pulses are required for the output to cycle, the T flip-flop divides the clock frequency by two and is often called a "divide-by-two" binary counter. In LabVIEW (see the block diagram and open the T flip-flop subVI), the T flip-flop is simulated with a Case structure placed inside a While Loop. The upper shift register, with the inverter, simulates the digital clock. If the output of one T flip-flop is used as the clock input for a second T flip-flop, the output frequency of the pair of flip-flops is (/2 and /2) or divide by 4. Load and run Binary2.vi. Figure 6-3. LabVIEW Simulation of a Divide-by-Four Binary Counter If the output of the first flip-flop is weighted as 1 and the second flip-flop as 2, the decimal equivalent values during clocking form the sequence 0,1,2,3, 0,1,2,3, 0,1,2,3, etc. This is a modulo 4 binary counter. In the LabVIEW simulation, note on the block diagram how the output of the first flip-flop is ANDed with the clock to become the input of the next flip-flop. Fundamentals of Digital Electronics 6-2 National Instruments Corporation Lab 6 JK Master-Slave Flip-Flop Binary Counters Binary counters are formed from J-K flip-flops by tying all the (J,K) inputs to a logic 1 (HI) and connecting the output of each flip-flop to the clock of the next flip-flop. The clock signal enters the chain at the clock of the first flip-flop, and the result ripples down the chain. Q0 Hi Hi Q1 Hi Q2 Hi Q3 J clock C K Q J C Q J C Q J C Q Q K Q K Q K Q Hi Hi Hi Hi Figure 6-4. 4-Bit Binary Counter Built with JK Flip-Flops In this configuration, the clock signal is divided by 2 each time it passes through a JK flip-flop. Four JKs in sequence divide by 24 or 16. Load the 4-bit binary VI called Binary4.vi, which simulates the above binary counter. By pressing the Run button, observe the operation of the divide-by-16 binary counter. The four binary states (Q3, Q2, Q1, Q0) are displayed as LED indicators, and the decimal equivalent value as a numeric on the front panel. In addition, the timing diagram is shown for the four outputs Q0-Q3 on four separate charts. National Instruments Corporation 6-3 Fundamentals of Digital Electronics Lab 6 JK Master-Slave Flip-Flop Figure 6-5. LabVIEW Simulation of a 4-Bit Binary Counter Observe the sequence and fill in the truth table below. Table 6-1. 4-Bit Binary Count Sequence and Decimal Equivalent Values Clock Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 Q3 0 Q2 0 Q1 0 Q0 0 DE # 0 1 1 1 1 15 Fundamentals of Digital Electronics 6-4 National Instruments Corporation Lab 6 JK Master-Slave Flip-Flop The complete table displays all binary combinations for a 4-bit binary counter. If the outputs Q0, Q1, Q2, and Q3 are weighted as 20, 21, 22, and 23, all the binary numbers 0-15 can be represented on the four outputs. Look at the LabVIEW block diagram to see how the decimal equivalent value is calculated. In hexadecimal counting, the 16 states (0-15) are labeled as 0...9 and A...F. This notation is more compact and easier to remember than long combinations of binary bits. Larger bit lengths are subdivided into groups of 4 bits called a nibble, and each nibble is coded as one hexadecimal character. Fo...
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This note was uploaded on 12/01/2009 for the course S ss taught by Professor S during the Spring '09 term at Universidad Autonoma de Nuevo Leon - School of Business.

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