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Unformatted text preview: mes along, the JK flipflop has true memory. When the J and K inputs are low, the state of the outputs Q and Q are unchanged on clocking. Thus, information can be placed onto the output bit and held until requested at a future time. The output Q can be clocked low or high by setting the (J,K) inputs to (0,1) or (1,0), respectively. In fact, placing an inverter between J and K inputs results in a Dlatch circuit. The schematic diagram for the JK flipflop and its truth table is shown below. Note that the JK flipflop can also be Set or Reset with direct logic inputs.
Set J clk K Clr Q Q clock J 0 0 1 1 K 0 1 0 1 Q Q no change 0 1 1 0 Set Clr 0 0 1 1 0 1 0 1 Q Q disallowed 1 0 0 1 toggle clocked clocked logic direct logic Figure 61. JK FlipFlop Logic Symbol and Truth Tables The first entry of the clocked truth table is the memory state, while the next two combinations are the latched states. What is new with the JK flipflop is the fourth combination (1,1), which produces a toggle state. On clocking, the output changes from [1>0] if 1 or [0>1] if 0. This complement function is often referred to as bit toggling, and the resulting flipflop (J and K inputs pulled HI) is called a T flipflop. Because only one toggle occurs per output cycle, it takes two clock cycles to return the output state to its initial state. Load Binary1.vi and observe the operation of the Tflipflop on clocking. National Instruments Corporation 61 Fundamentals of Digital Electronics Lab 6 JK MasterSlave FlipFlop Figure 62. LabVIEW Simulation of a DividebyTwo Counter Using a T FlipFlop SubVI Each time the Run button is pressed, the clock changes state from HILO or LOHI. How many times do you need to press the Run button to cycle the output bit from LOHILO? It may be easier to make the correct observation by pressing the Run Continuously button. Because two clock pulses are required for the output to cycle, the T flipflop divides the clock frequency by two and is often called a "dividebytwo" binary counter. In LabVIEW (see the block diagram and open the T flipflop subVI), the T flipflop is simulated with a Case structure placed inside a While Loop. The upper shift register, with the inverter, simulates the digital clock. If the output of one T flipflop is used as the clock input for a second T flipflop, the output frequency of the pair of flipflops is (/2 and /2) or divide by 4. Load and run Binary2.vi. Figure 63. LabVIEW Simulation of a DividebyFour Binary Counter If the output of the first flipflop is weighted as 1 and the second flipflop as 2, the decimal equivalent values during clocking form the sequence 0,1,2,3, 0,1,2,3, 0,1,2,3, etc. This is a modulo 4 binary counter. In the LabVIEW simulation, note on the block diagram how the output of the first flipflop is ANDed with the clock to become the input of the next flipflop. Fundamentals of Digital Electronics 62 National Instruments Corporation Lab 6 JK MasterSlave FlipFlop Binary Counters
Binary counters are formed from JK flipflops by tying all the (J,K) inputs to a logic 1 (HI) and connecting the output of each flipflop to the clock of the next flipflop. The clock signal enters the chain at the clock of the first flipflop, and the result ripples down the chain. Q0 Hi Hi Q1 Hi Q2 Hi Q3 J clock C K Q J C Q J C Q J C Q Q K Q K Q K Q Hi Hi Hi Hi Figure 64. 4Bit Binary Counter Built with JK FlipFlops In this configuration, the clock signal is divided by 2 each time it passes through a JK flipflop. Four JKs in sequence divide by 24 or 16. Load the 4bit binary VI called Binary4.vi, which simulates the above binary counter. By pressing the Run button, observe the operation of the divideby16 binary counter. The four binary states (Q3, Q2, Q1, Q0) are displayed as LED indicators, and the decimal equivalent value as a numeric on the front panel. In addition, the timing diagram is shown for the four outputs Q0Q3 on four separate charts. National Instruments Corporation 63 Fundamentals of Digital Electronics Lab 6 JK MasterSlave FlipFlop Figure 65. LabVIEW Simulation of a 4Bit Binary Counter Observe the sequence and fill in the truth table below.
Table 61. 4Bit Binary Count Sequence and Decimal Equivalent Values Clock Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 Q3 0 Q2 0 Q1 0 Q0 0 DE # 0 1 1 1 1 15 Fundamentals of Digital Electronics 64 National Instruments Corporation Lab 6 JK MasterSlave FlipFlop The complete table displays all binary combinations for a 4bit binary counter. If the outputs Q0, Q1, Q2, and Q3 are weighted as 20, 21, 22, and 23, all the binary numbers 015 can be represented on the four outputs. Look at the LabVIEW block diagram to see how the decimal equivalent value is calculated. In hexadecimal counting, the 16 states (015) are labeled as 0...9 and A...F. This notation is more compact and easier to remember than long combinations of binary bits. Larger bit lengths are subdivided into groups of 4 bits called a nibble, and each nibble is coded as one hexadecimal character. Fo...
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This note was uploaded on 12/01/2009 for the course S ss taught by Professor S during the Spring '09 term at Universidad Autonoma de Nuevo Leon  School of Business.
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