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Unformatted text preview: adds two 4-bit numbers with carry in) Four-bit Adder2.vi (simplified version) Four-bit Adder3.vi (uses Boolean arrays for inputs and outputs) Eight-bit Adder.vi (uses two 4-bit adders) Fundamentals of Digital Electronics 3-6 National Instruments Corporation Lab 4 Memory: The D-Latch
In the first three labs in this series, all your work has been with combinational circuits in which the input states completely determine the output states. In the circuits thus far, there is no dependence on past history or how you arrived at the current state. This means that "remembering" cannot be built into the circuits. Most digital operations are sequential, in that event B must occur after event A. Furthermore, in a digital computer, events are not only sequential but also synchronous with some external clock. Clocked logic devices are devices whose output changes only when a clock signal is asserted. In the next few labs, you will see how the addition of clocked logic devices brings memory into digital circuits, making it possible to construct many interesting digital circuits. One simple memory circuit is called the data latch, or D-latch. This is a device which, when "told" to do so via the clock input, notes the state of its input and holds that state at its output. The output state remains unchanged even if the input state changes, until another update request is received. Traditionally, the input of the D-latch is designated by D and the latched output by Q. The update command is provided by asserting the clock input in the form of a transition (from HI to LO) or (from LO to HI), so-called edge-triggered devices or level triggered devices, where the output follows the input whenever the clock is HI. National Instruments Corporation 4-1 Fundamentals of Digital Electronics Lab 4 Memory: The D-Latch PreSet D D Clock Clr Q 0 1 Q Q Q 0 1 1 0 Set Clr 0 0 1 1 0 1 0 1 Q Q disallowed 1 0 0 1 clocked logic clocked Figure 4-1. D-Latch Symbol and Truth Tables Data present on the input D is passed to the outputs Q and Q when the clock is asserted. The truth table for an edge-triggered D-latch is shown to the right of the schematic symbol. Some D-latches also have Preset and Clear inputs that allow the output to be set HI or LO independent of the clock signal. In normal operation, these two inputs are pulled high so as not to interfere with the clocked logic. However, the outputs Q and Q can be initialized to a known state, using the Preset and Clear inputs when the clocked logic is not active. Figure 4-2. LabVIEW Simulation of a D-Latch In LabVIEW, you can simulate the D-latch with a shift register added to a While Loop. The up-arrow block is the D input, and the down-arrow block is the output Q. The complement is formed with an inverter tied to the Q output. The clock input is analogous with the loop index [i]. You can use a Boolean constant outside the loop to preset or clear the output. D Latch.vi, shown above, uses an unwired conditional terminal to ensure that the D-latch executes only once when it is called. Shift Registers
In digital electronics, a shift register is a cascade of 1-bit memories in which each bit is updated on a clock transition by copying the state of its neighbor. Fundamentals of Digital Electronics 4-2 National Instruments Corporation Lab 4 Memory: The D-Latch Q1 Q2 Q3 Q4 HI or LO D Q D Q D Q D Q Q Clock Q Q Q Figure 4-3. 4-Bit Shift Register The bits at the ends have only one neighbor. The input bit D is "fed" from an external source (HI or LO), and the output Q4 spills off the other end of the shift register. Here is an example of a 4-bit shift register whose initial output state is  and input is :
Clock Cycle n n+1 n+2 n+3 n+4 Q1 0 1 1 1 1 Q2 0 0 1 1 1 Q3 0 0 0 1 1 Q4 0 0 0 0 1 To "cascade" D-latches as above in LabVIEW, additional elements are added to the D-latch shift register. For example, here is the 4-bit register. Shift.vi executes the above sequence. Figure 4-4. Block Diagram for an 8-Bit Shift Register It is a simple matter to add additional elements to simulate larger width shift registers. The following VI, Bucket.vi, simulates a "bucket brigade" where a single bit is introduced on the input D and propagates down the line, where it spills out and is lost after passing Q8. National Instruments Corporation 4-3 Fundamentals of Digital Electronics Lab 4 Memory: The D-Latch Figure 4-5. Front Panel of an 8-Bit Shift Register Simulation LabVIEW Challenge
Design a VI in which after the "bucket" passes the last bit, a new bucket is added at the input D, and the process continues forever. Ring Counters
If the output of a shift register is "fed" back into the input, after n clock cycles, the parallel output eventually will repeat and the shift register now becomes a counter. The name ring counter comes from looping the last output bit back into the input. A simple 4-bit ring counter takes the last output, Q4, and loops it back directly to the input of the shift r...
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This note was uploaded on 12/01/2009 for the course S ss taught by Professor S during the Spring '09 term at Universidad Autonoma de Nuevo Leon - School of Business.
- Spring '09