14 q sc r q c q delay latch d latch d d q c s q d s

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Unformatted text preview: C (a ) Q R S R la tc h (b ) Figure 6.15 D Latch Characteristics E n a b le in p u t C 0 0 1 1 1 1 E x c ita tio n in p u t D × ´ 0 0 1 1 P resen t sta te Q 0 1 0 1 0 1 (a ) N ext sta te Q* 0 1 0 0 1 1 H o ld S to re 0 S to re 1 0d,10 0 10 (b ) CD 11 1 0d,11 Figure 6.16 Q* = DC + C′ Q D Latch Timing Diagram D C Q E n a b le d E n a b le d H o ld H o ld E n a b le d Figure 6.17 D Latch Timing Constraints D m ay not change D C Q M in im u m e n a b le p u ls e w id th S e tu p tim e v io la tio n H o ld tim e v io la tio n (h o ld ) (s e tu p ) th tsu tsu th tw U n k n o w n s ta te Figure 6.18 The SN74LS75 D Latch D C CD Q Q 1 CQ (a) (b ) D C 0 0 Q Q D C 1 Q 0 0 Q D C Q (c) Dt (d ) Q* Figure 6.19 Propagation Delays and Time Constraints for the SN74LS75 Hazard-Free D Latch, the SN74116 D 1 Q 1 C (a ) D C Q Q C1 C2 D (b ) P R E (o r S ) 1 1 Q 1 C 1 1 1 D Q Q C L R (o r R ) (c) (d ) Figure 6.20 Q* = DC + C′ Q + DC Master-Slave SR Flip-flop M a ste r S S C R R Q Q Q M S la v e S C R Q Q Q Q S C R Q (b ) Q C (c...
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This note was uploaded on 12/01/2009 for the course 123 123 taught by Professor Alpha during the Spring '09 term at Georgia Tech.

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