29 sn7474 flip flop timing specifications t o o u tp

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Unformatted text preview: L tP LH tP H L tP LH tP H L (b ) In p u t P in tPH L (a ) tPLH D D C lo c k C lo c k CLR PRE M in im u m V a lu e (n s) 20 5 30 37 30 30 V a lu e (n s) 25 40 25 40 25 40 C Q C o n s tra in t tsu th tw lo w tw h ig h tw lo w tw lo w (c) Figure 6.30 SN74175 Positive-Edge-Triggered D Flip-Flop 1D (4 ) D CK Q CLEAR Q (2 ) (3 ) 1Q 1Q 2D (5 ) D CK Q (7 ) (6 ) 2Q 2Q Q CLEAR 3D (1 2 ) D CK Q (1 0 ) (1 1 ) 3Q 3Q Q CLEAR 4D CLO CK CLEAR (9 ) (1 ) (1 3 ) D CK Q (1 5 ) (1 4 ) 4Q 4Q Q CLEAR (a ) Figure 6.31 (a) SN74273 Positive-Edge-Triggered D Flip-Flop 1D CLO CK (1 1 ) (3 ) 2D (4 ) 3D (7 ) 4D (8 ) 5D (1 3 ) 6D (1 4 ) 7D (1 7 ) 8D (1 8 ) 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R CLEAR (1 ) (2 ) 1Q (5 ) 2Q (6 ) 3Q (b ) (9 ) 4Q (1 2 ) 5Q (1 5 ) 6Q (1 6 ) 7Q (1 9 ) 8Q Figure 6.31 (b) SN74LS73A Edge-Triggered JK Flip-Flop Logic Diagram Q Q CLR K J CLK Figure 6.32 (a) SN74LS73A Logic Symbols 'L S 7 3 A 1J 1C L K 1 K 1C L R (1 4 ) (1 ) (3 ) (2 ) 1J C 1 1 K R (1 2 ) 1Q J C K CL R (1 3 ) Q Q 1Q (b...
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