7 nand sr latch s s n1 q s0 s1 q r r n2 a q r0 r1

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Unformatted text preview: b ) Q S Q R (c) Q S Q S Q R (d ) Q R (e) Q Figure 6.8 Set-Reset Latch Timing Diagram S R Q Q Set R eset Set Ille g a l in p u ts U n k n o w n v a lu e s (a ) S R Q Q Set R eset Set Ille g a l in p u ts U n k n o w n v a lu e s (b ) Figure 6.9 SR Latch Propagation Delays S R Q Q tP LH (S to Q ) tP LH (N 2 ) tPH L ( R to Q ) tPH L (N 2 ) tPH L (N 1 ) tPLH (N 1 ) SR Latch Characteristics 0d 0 01 (b ) N o change R eset Set N o t a llo w e d Q 1 1 0 R (c) Ð 1 Q 0 SR 00 0 01 0 11 Ð S 10 1 SR 10 E x c ita tio n in p u ts S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 P resen t sta te Q 0 1 0 1 0 1 0 1 (a ) N ext s ta te Q* 0 1 0 0 1 1 × × 1 d0 Figure 6.11 Q* = S + R′ Q SN74279 Latch with Two Set Inputs S1 S2 S1 S2 Q Q R R (a ) (b ) Q Figure 6.12 Gated SR Latch S S S C *S C R (b ) S C R (d ) Q Q Q Q R C* R (c) Q S Q S Q C R (a ) Q C R R Figure 6.13 Gated SR Latch Characteristics E n a b le in p u ts C 0 0 1 1 1 1 1 1 1 1 × ´ 0 0 0 0 1 1 1 1 E x c ita tio n in p u ts S R × ´ 0 0 1 1 0 0 1 1 P resen t s ta te Q 0 1 0 1 0 1 0 1 0 1 (a ) N ext sta te Q* 0 1 0 1 0 0 1 1 × × H o ld N o change R eset S et N o t a llo w e d 0dd,10d 0 101 (b ) C SR 110 1 0dd,1d0 Figure 6.14 Q* = SC + R′ Q + C′ Q Delay Latch (D latch) D D Q C S Q D S Q C Q Q R S R la t c h (c)...
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This note was uploaded on 12/01/2009 for the course 123 123 taught by Professor Alpha during the Spring '09 term at Georgia Institute of Technology.

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