chapter_6 - Chapter 6 -- Introduction to Sequential Devices...

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Unformatted text preview: Chapter 6 -- Introduction to Sequential Devices The Sequential Circuit Model x1 xn C o m b in a tio n a l lo g ic (a ) z1 zm x1 xn C o m b in a tio n a l lo g ic z1 zm y1 yr Y r Y 1 M e m o ry (b ) Figure 6.1 State Tables and State Diagrams In p u t P re s e n t s ta te x N e x t s ta te x /z y N ext s ta te /o u tp u t (a ) (b ) Y In p u t/o u tp u t P re se n t sta te y Y /z Figure 6.2 Sequential Circuit Example In p u t x 0 P resen t s ta te A B C D D B C A (a ) 0 /1 1 /1 A C /0 /1 /1 /0 C A D B 1 /1 /0 /0 /1 1 /0 0 /0 0 /0 1 /0 B 0 /1 1 /1 x /z (b ) D Figure 6.3 Latch and Flip-flop Timing S et R eset Q (a ) Set R eset C lo c k Q (b ) Figure 6.4 TTL Memory Elements Set Latch 0 0 (a ) 0 0 S 0 (b ) 0 Q S 1 1 (c) 1 Q S 1 0 (d ) 1 Q Figure 6.5 Reset Latch 0 S 0 (a ) 1 0 Q 0 R=0 1 0 1 Q 1 R=1 0 1 0 Q (b ) (c) 1 R=0 0 1 0 Q R Q Q (e) (d ) Figure 6.6 Set-Reset Latch (SR latch) S N1 Q N2 (a ) S Q S R (b ) N1 Q N2 Q N1 Q S R (d ) Q Q R N2 (c) Q Figure 6.7 NAND SR Latch S S N1 Q S=0 S=1 Q R R N2 (a ) Q R=0 R=1 (b ) Q S Q R (c) Q S Q S Q R (d ) Q R (e) Q Figure 6.8 Set-Reset Latch Timing Diagram S R Q Q Set R eset Set Ille g a l in p u ts U n k n o w n v a lu e s (a ) S R Q Q Set R eset Set Ille g a l in p u ts U n k n o w n v a lu e s (b ) Figure 6.9 SR Latch Propagation Delays S R Q Q tP LH (S to Q ) tP LH (N 2 ) tPH L ( R to Q ) tPH L (N 2 ) tPH L (N 1 ) tPLH (N 1 ) SR Latch Characteristics 0d 0 01 (b ) N o change R eset Set N o t a llo w e d Q 1 1 0 R (c) Ð 1 Q 0 SR 00 0 01 0 11 Ð S 10 1 SR 10 E x c ita tio n in p u ts S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 P resen t sta te Q 0 1 0 1 0 1 0 1 (a ) N ext s ta te Q* 0 1 0 0 1 1 × × 1 d0 Figure 6.11 Q* = S + R′ Q SN74279 Latch with Two Set Inputs S1 S2 S1 S2 Q Q R R (a ) (b ) Q Figure 6.12 Gated SR Latch S S S C *S C R (b ) S C R (d ) Q Q Q Q R C* R (c) Q S Q S Q C R (a ) Q C R R Figure 6.13 Gated SR Latch Characteristics E n a b le in p u ts C 0 0 1 1 1 1 1 1 1 1 × ´ 0 0 0 0 1 1 1 1 E x c ita tio n in p u ts S R × ´ 0 0 1 1 0 0 1 1 P resen t s ta te Q 0 1 0 1 0 1 0 1 0 1 (a ) N ext sta te Q* 0 1 0 1 0 0 1 1 × × H o ld N o change R eset S et N o t a llo w e d 0dd,10d 0 101 (b ) C SR 110 1 0dd,1d0 Figure 6.14 Q* = SC + R′ Q + C′ Q Delay Latch (D latch) D D Q C S Q D S Q C Q Q R S R la t c h (c) C (a ) Q R S R la tc h (b ) Figure 6.15 D Latch Characteristics E n a b le in p u t C 0 0 1 1 1 1 E x c ita tio n in p u t D × ´ 0 0 1 1 P resen t sta te Q 0 1 0 1 0 1 (a ) N ext sta te Q* 0 1 0 0 1 1 H o ld S to re 0 S to re 1 0d,10 0 10 (b ) CD 11 1 0d,11 Figure 6.16 Q* = DC + C′ Q D Latch Timing Diagram D C Q E n a b le d E n a b le d H o ld H o ld E n a b le d Figure 6.17 D Latch Timing Constraints D m ay not change D C Q M in im u m e n a b le p u ls e w id th S e tu p tim e v io la tio n H o ld tim e v io la tio n (h o ld ) (s e tu p ) th tsu tsu th tw U n k n o w n s ta te Figure 6.18 The SN74LS75 D Latch D C CD Q Q 1 CQ (a) (b ) D C 0 0 Q Q D C 1 Q 0 0 Q D C Q (c) Dt (d ) Q* Figure 6.19 Propagation Delays and Time Constraints for the SN74LS75 Hazard-Free D Latch, the SN74116 D 1 Q 1 C (a ) D C Q Q C1 C2 D (b ) P R E (o r S ) 1 1 Q 1 C 1 1 1 D Q Q C L R (o r R ) (c) (d ) Figure 6.20 Q* = DC + C′ Q + DC Master-Slave SR Flip-flop M a ste r S S C R R Q Q Q M S la v e S C R Q Q Q Q S C R Q (b ) Q C (c lo c k ) (a ) C M a s te r S la v e S R Q M g a te d h o ld h o ld g a te d g a te d h o ld h o ld g a te d g a te d h o ld h o ld g a te d g a te d h o ld h o ld g a te d S and R m ay not change R S C tsu (s e tu p ) th (h o ld ) tw C lo w p u lse w id th ( m a s te r e n a b le d ) tw C h ig h p u ls e w id th ( s la v e e n a b le d ) (d ) Q F lip -flo p o u tp u t c a n c h a n g e (c ) Figure 6.20 SR Master-Slave Flip-Flop Characteristics S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 C Q* 0 1 0 0 1 1 N o change R eset 0 Set 01 (b ) 0d SR 10 1 0d × N o t a llo w e d × (a ) Figure 6.22 Q* = S + R′ Q Master-Slave D Flip-Flop M a ste r D D Q Q M S la v e D Q Q D Q C Q C Q Q C Q C (c lo c k ) (a ) (b ) Figure 6.23 Master-Slave D Flip-Flop Characteristics D 0 0 1 1 Q 0 1 0 1 (a ) C Q* 0 0 1 1 S to r e 0 S to r e 1 0 0 0 (b ) D 1 1 1 E n a b le d : C D Q Q=Q M S M S M S M S M M S (c) Figure 6.24 Q* = D Pulse-Triggered JK Flip-Flop Characteristics 0d 0 H o ld R eset S et T o g g le Q 1 1 0 K (c) 0 1 Q 0 JK 00 0 01 0 11 1 d1 (b ) J 10 1 JR 1d J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 (a ) C Q* 0 1 0 0 1 1 1 0 1 d0 Figure 6.25 Q* = K′ Q + JQ′ Pulse-Triggered JK Flip Realization KQ K J JQ C (b ) (a ) C Q Q Q* D Q Q J C K Q Q Figure 6.26 The SN7476 Dual Pulse-Triggered JK Flip-Flop '7 6 1PRE 1J 1CLK J C K Q CLR (a ) PRE Q Q Q 2PRE 2J 2CLK 2K 2CLR 1K 1CLR (2 ) (4 ) (1 ) (1 6 ) (3 ) S 1J C1 1K R (1 5 ) 1Q (1 4 ) 1Q (7 ) (9 ) (6 ) (1 2 ) (8 ) (1 0 ) 2Q (1 1 ) 2Q (b ) Figure 6.27 SN7474 Dual Positive-Edge-Triggered D Flip-Flop '7 4 PRE 1PRE 1CLK CLR Q Q Q CLK Q CLR (b ) D (a ) (c) PRE Q Q 1D 1CLR (4 ) (3 ) (2 ) (1 ) S C1 1D R (5 ) 1Q (6 ) 1Q 2PRE 2CLK 2D 2CLR (1 0 ) (1 1 ) (1 2 ) (1 3 ) (9 ) 2Q (8 ) 2Q Figure 6.28 SN7474 Excitation Table In p u ts PRE L H L H H H CLR H L L H H H D × × × H L × CLK × × × ↑ ↑ L Q O u tp u ts Q L H H L H Q0 M ode S et C le a r N o t a llo w e d C lo c k e d o p e ra tio n C lo c k e d o p e ra tio n H o ld H L H H L Q0 Figure 6.29 SN7474 Flip-Flop Timing Specifications T o O u tp u t Q fro m : D sh o u ld b e s ta b le th D tsu tsu C lo c k PRE th CLR D e la y P a ra m e te r tP LH tP H L tP LH tP H L tP LH tP H L (b ) In p u t P in tPH L (a ) tPLH D D C lo c k C lo c k CLR PRE M in im u m V a lu e (n s) 20 5 30 37 30 30 V a lu e (n s) 25 40 25 40 25 40 C Q C o n s tra in t tsu th tw lo w tw h ig h tw lo w tw lo w (c) Figure 6.30 SN74175 Positive-Edge-Triggered D Flip-Flop 1D (4 ) D CK Q CLEAR Q (2 ) (3 ) 1Q 1Q 2D (5 ) D CK Q (7 ) (6 ) 2Q 2Q Q CLEAR 3D (1 2 ) D CK Q (1 0 ) (1 1 ) 3Q 3Q Q CLEAR 4D CLO CK CLEAR (9 ) (1 ) (1 3 ) D CK Q (1 5 ) (1 4 ) 4Q 4Q Q CLEAR (a ) Figure 6.31 (a) SN74273 Positive-Edge-Triggered D Flip-Flop 1D CLO CK (1 1 ) (3 ) 2D (4 ) 3D (7 ) 4D (8 ) 5D (1 3 ) 6D (1 4 ) 7D (1 7 ) 8D (1 8 ) 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R CLEAR (1 ) (2 ) 1Q (5 ) 2Q (6 ) 3Q (b ) (9 ) 4Q (1 2 ) 5Q (1 5 ) 6Q (1 6 ) 7Q (1 9 ) 8Q Figure 6.31 (b) SN74LS73A Edge-Triggered JK Flip-Flop Logic Diagram Q Q CLR K J CLK Figure 6.32 (a) SN74LS73A Logic Symbols 'L S 7 3 A 1J 1C L K 1 K 1C L R (1 4 ) (1 ) (3 ) (2 ) 1J C 1 1 K R (1 2 ) 1Q J C K CL R (1 3 ) Q Q 1Q (b ) (7 ) 2J 2 C L (5 ) K 2 (1 0 ) K 2 C L (6 ) R (c ) (9 ) 2Q (8 ) 2Q Figure 6.32 (b) and (c) SN74276 and SN74111 Edge-Triggered JK Flip-Flops '2 7 6 P R E (1 1 ) C L K (1 ) (2 ) (3 ) (4 ) (9 ) (8 ) (7 ) (1 2 ) (1 3 ) (1 4 ) (1 9 ) (1 8 ) (1 7 ) S R (5 ) 1PRE 1J 1Q 1C LK 1K 2Q 1C LR 2PRE 3Q 2J 2C LK 4Q 2K 2C LR (d ) (2 ) (4 ) (5 ) (1 ) (3 ) (1 4 ) (1 2 ) (1 1 ) (1 5 ) (1 3 ) (1 0 ) S 1J C 1 1 K R (9 ) (7 ) 1Q '1 1 1 1C 2C 3C 4C 1J LK 1K 2J LK 2K 3J LK 3K 4J LK 4K 1J C 11 K (6 ) (6 ) 1Q (1 5 ) 2Q (1 6 ) 2Q (e ) Figure 6.32 (d) and (e) Negative-Edge-Triggered T Flip-Flop V C C PRE Q T Q CLR J C K PRE Q Q CLR (a ) (b ) Figure 6.33 Edge-Triggered T Flip-Flop Characteristics 0 T Q 0 1 (a ) Q* 1 0 T o g g le T o g g le 0 T 1 1 1 (b ) 0 Figure 6.34 Q* = Q′ Clocked T Flip-Flop PRE T C CLR Q Q T J C K PRE Q Q CLR (a ) (b ) Figure 6.35 Excitation Table for Clocked T Flip-Flops T 0 0 1 1 Q 0 1 0 1 C ↓ ↓ ↓ ↓ Q* 0 1 1 0 H o ld T o g g le Figure 6.36 Q* = T′ Q + TQ′ The Clocked T Flip-Flop Timing Diagram C lo c k Q T C lo c k c ε Dt c Q T T T Q (a ) Q Q Q (b ) Figure 6.37 Summary of Latch and Flip-Flop Characteristics SE555 Precision Timing Module V R eset CC C o n tro l R T h re sh o ld C1 SE 555 R1 R S 1 Q O u tp u t R C2 T rig g e r R C o m p a ra to r Q1 G ro u n d D is c h a rg e Figure 6.38 Astable Operation of The SE555 V CC 0 .0 1 m F R 5 A 8 V CC C ont 4 7 RESET D IS C H THRES T R IG GND 1 R L R 6 B O ut 3 S q u a re w a v e 2 C SE 555 Figure 6.39 Monostable (One shot) Device Realization V CC 0 .0 1 m F R 5 A 8 VCC C ont 4 7 6 RESET D IS C H THRES T R IG R L O ut 3 O u tp u t T rig g e r 2 C SE 555 GND 1 R A 3 .3 -m s p u ls e if = 3 kO hm and C = 1 m F Figure 6.40 PROM-based Sequential Circuits In p u t x PRO M 1 PRO M 2 N ext s ta te Y R e g is te r O u tp u t z C lo c k P r e s e n t s ta te In p u t P resen t s ta te x (a ) y C o n te n ts PRO M x A d d ress y PRO M 1 Y PRO M 2 z y Y /z N e x t sta te / o u tp u t (b ) (c) Figure 6.41 PROM-based Sequential Circuit Example x y 2y 1 00 01 10 11 0 1 1 0 0 0 /1 1 /0 1 /1 0 /0 Y 2Y 1/z (a ) 0 1 0 1 0 1 0 1 /1 /1 /0 /0 1 x 0 1 2 3 y2 y1 4 5 6 7 x 0 0 0 0 1 1 1 1 y2 0 0 1 1 0 0 1 1 y1 0 1 0 1 0 1 0 1 (b ) Y 1 1 0 0 0 1 0 1 2 1 1 0 0 0 1 0 1 Y2 D Q 0 1 1 0 0 1 0 1 Y 1 1 0 1 0 1 1 0 0 z Y 0 1 1 0 0 1 0 1 1 z 1 0 1 0 1 1 0 0 C D Q C C lo c k (c) Figure 6.41 Prime Number Sequencer 256 x 8 PR O M 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 Figure 6.43 251 252 253 254 255 0 0 0 0 0 0 1 0 1D 1Q 2D 2Q 3D 3Q 4D 4Q 5D 5Q 6D 6Q 7D 7Q 8D 8Q C lo c k C lo c k SN 74273 ( 8 D flip -flo p s ) ...
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