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# chapter_6 - Chapter 6 Introduction to Sequential Devices...

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Chapter 6 -- Introduction to Sequential Devices

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The Sequential Circuit Model x 1 z 1 x n z m ( a ) y 1 Y r y r Y 1 M e m o r y C o m b i n a t i o n a l l o g i c C o m b i n a t i o n a l l o g i c ( b ) x 1 z 1 x n z m Figure 6.1
State Tables and State Diagrams P r e s e n t s t a t e I n p u t ( a ) ( b ) I n p u t / o u t p u t P r e s e n t s t a t e N e x t s t a t e y x Y / z x / z N e x t s t a t e / o u t p u t y Y Figure 6.2

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Sequential Circuit Example 1 / 1 P r e s e n t s t a t e A C B D ( a ) ( b ) 0 1 0 / 1 0 / 0 1 / 1 x / z I n p u t x 0 / 0 1 / 0 1 / 0 D / 0 B / 1 C / 1 A / 0 C / 1 A / 0 D / 0 B / 1 A B C D 0 / 1 Figure 6.3
Latch and Flip-flop Timing S e t R e s e t ( a ) ( b ) C l o c k Q S e t R e s e t Q Figure 6.4

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TTL Memory Elements
Set Latch ( a ) ( b ) ( c ) ( d ) 0 0 0 S Q 0 0 0 1 S Q 1 1 1 S Q 0 1 Figure 6.5

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Reset Latch ( d ) ( e ) 1 0 Q R R = 0 Q Q 1 ( c ) 1 0 Q R = 1 1 ( b ) 0 1 Q R 0 ( a ) 0 1 Q 0 0 0 1 0 S Figure 6.6
Set-Reset Latch (SR latch) ( a ) ( c ) ( d ) S Q N 1 N 2 Q ( b ) S Q N 1 N 2 Q R S R Q Q N 1 N 2 Q Q S R Figure 6.7

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NAND SR Latch ( b ) ( d ) Q R = 0 R = 1 S S Q ( a ) Q R R S S Q N 1 N 2 ( c ) Q R S Q Q Q R S ( e ) Q Q R S Figure 6.8
Set-Reset Latch Timing Diagram ( a ) S R Q S e t R e s e t I l l e g a l i n p u t s U n k n o w n v a l u e s Q S e t ( b ) S R Q S e t R e s e t I l l e g a l i n p u t s U n k n o w n v a l u e s Q S e t Figure 6.9

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SR Latch Propagation Delays S R Q t P L H ( S t o Q ) t P L H ( N 2 ) t P H L ( N 1 ) t P H L ( R Q ) t P H L ( N 2 ) t P L H ( N 1 ) Q
SR Latch Characteristics S R Q Q * ( a ) E x c i t a t i o n i n p u t s P r e s e n t s t a t e N e x t s t a t e 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 × × N o c h a n g e R e s e t S e t N o t a l l o w e d Q S R 0 0 0 0 1 1 1 1 0 R Q 0 Ð 1 1 0 Ð 1 S 0 1 1 0 0 1 0 d d 0 ( b ) S R 0 1 ( c ) Figure 6.11 Q* = S + R Q

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SN74279 Latch with Two Set Inputs ( b ) ( a ) Q Q R Q R S 1 S 2 S 1 S 2 Figure 6.12
Gated SR Latch ( a ) C * R S C R S R Q Q ( b ) ( c ) Q Q C * S S C R S R Q Q S C R S C R Q Q ( d ) Figure 6.13

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Gated SR Latch Characteristics E x c i t a t i o n i n p u t s S R N e x t s t a t e Q * 0 0 1 1 1 1 1 1 1 1 × ´ 0 0 0 0 1 1 1 1 E n a b l e i n p u t s C × ´ 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 × × H o l d N o c h a n g e R e s e t S e t N o t a l l o w e d P r e s e n t s t a t e Q 1 1 0 1 0 1 0 d d , 1 0 d 0 d d , 1 d 0 ( a ) ( b ) C S R 0 1 Figure 6.14 Q * = SC + R Q + C Q
Delay Latch (D latch) ( b ) Q Q D C S R S R l a t c h ( c ) Q Q D C S R D C Q Q ( a ) Figure 6.15

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D Latch Characteristics E x c i t a t i o n i n p u t D N e x t s t a t e Q * 0 0 1 1 1 1 E n a b l e i n p u t C × ´ 0 0 1 1 0 1 0 1 0 1 0
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chapter_6 - Chapter 6 Introduction to Sequential Devices...

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