ecse221_as3 - Department of Electrical Engineering...

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Department of Electrical Engineering Introduction to Computer Engineering I Assignment 3: Sequential Logic Due: Monday, October 27 th at 5:00pm (6 th floor assignments box) Question 1 Consider 3 implementations of an S-R flip-flop using a clocked latch, master-slave and edge triggered circuits. Even though all 3 can be described by the same state transition table, their timing behaviours are quite different. Begin by implementing each of the 3 circuits in LogicWorks. Devise a single set of waveforms, (S, R, Clk, Pr, Clr), that verifies the state transition table for an S-R flip-flop for each of the 3 implementations. In other words, connect the S, R, Clk, Pr, and Clr inputs for each of the circuits together and run them off of the same inputs. Make sure to invert (negate) the clock input of the master-slave so that all outputs change relative to the same edge. Each of the 3 flip-flops can be differentiated on the basis of its timing behaviour. Devise a LogicWorks simulation that differentiates each of the 3 flip-flop types and explain the differences with respect to the outputs. Generating Waveforms in LogicWorks LogicWorks can read in an externally generated set of timing signals for use as inputs to a simulated circuit. The format is a file of ASCII text and is described in Appendix D of the LogicWorks manual., but the following example should be sufficient to get you going for this assignment. Consider the clocked S-R latch shown below. 0 1 0 1 Q' Q S Clock R In order to generate the Clock, S, and R input waveforms all you need to do is to create a text file using your favourite text editor or spreadsheet program (but remember to save the resulting file
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as text!). The format of the timing file is tab-delimited (i.e. seperated by tab characters) text. In fact, this is particularly well-suited to spreadsheet programs like Quattro or Excel. The timing file is in the form of a table with the first line defining the header information (remember, each entry must be seperated by a tab character and each line in the file must be delimited by a carriage return). The first two entries, $T and $D, are manditory and represent the absolute time and the delay to the next time step respectively. The remaining entries, $I Clk, $I S, and $I R, define the 3 variables for which timing information is to be generated. $T $D $I Clk $I S $I R 0 5 0 0 0 5 5 0 0 1 10 5 1 0 1 15 5 0 0 1 20 10 0 0 0 30 5 1 0 0 35 10 0 0 0 45 5 0 1 0 50 5 1 1 0 55 5 0 1 0 60 5 0 0 0 65 5 0 0 1 70 5 1 0 1 75 5 0 0 1 80 5 0 0 0 90 5 1 0 0 95 15 0 0 0 110 5 1 0 0 115 10 0 0 0 For example, the second line in the file specifies that at T=0, variables Clk, S, and R take on values of 0,0, and 0 respectively. The D entry is 5 and specifies that the next time step will occur at T=T+5, i.e. T=5. Once your file is prepared, run your simulation and in the timing window open the file using the
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ecse221_as3 - Department of Electrical Engineering...

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