EE101Discussion11

EE101Discussion11 - © Mark Redekopp, All rights reserved...

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Unformatted text preview: © Mark Redekopp, All rights reserved Digital Design Process Flow Mark Redekopp © Mark Redekopp, All rights reserved Progression of Logic Density • Small Scale Integrated (SSI) Circuits – 1960‟s and 1970‟s – A few gates on a chip • Medium Scale Integrated (MSI) Circuits – 1970‟s – Around a hundred gates per chip („283s and ‟85s) • Very Large Scale Integrated (VLSI) Circuits – 100‟s of million gates © Mark Redekopp, All rights reserved Digital Circuit Design Steps • Description – Design and computer-entry of circuit • Verification – Simulate design for correctness • Synthesis – Determine components/gates and their connections • Place and Route – Determine the physical placement and wire connections between components on actual silicon • ASIC Fabrication / FPGA implementation © Mark Redekopp, All rights reserved Digital Circuit Design Design Files Simulator Component Netlist Input Stimulus (Testbench) Synthesis Place and Route Meets Constraints Design Correct FPGA configuration / ASIC netlist Meets Constraints © Mark Redekopp, All rights reserved Step 1: Description • Much of the design process is done by a computer • Human designers must describe and capture their circuits into a format a computer can use • 2 common entry forms: – Schematic Entry: computerized drawing of the gates and components and their connections – HDL (Hardware Description Language): text description of circuit (similar to programming languages) © Mark Redekopp, All rights reserved...
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This note was uploaded on 12/02/2009 for the course EE 101 at USC.

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EE101Discussion11 - © Mark Redekopp, All rights reserved...

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