EE101Lecture11

EE101Lecture11 - Introduction to Digital Logic Lecture 11:...

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© Mark Redekopp, All rights reserved Introduction to Digital Logic Lecture 11: Cascading Decoders Implementing Functions w/ Decoders Encoders & Priority Encoders
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© Mark Redekopp, All rights reserved Decoder w/ Multiple Enables When a decoder has multiple enables, all enables must be active for the decoder to be enabled D0 D1 D2 D3 D4 D5 D6 D7 X (MSB) Y Z (LSB) E /G2 /G1 3 Enables /G1 must equal 0 /G2 must equal 0 and E must equal 1 Overall enable /G1 /G2 E
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© Mark Redekopp, All rights reserved Building Larger Decoders • Using the “building - block methodology”, cascade smaller decoders to build larger ones • We‟ll use stages of decoders The output of each decoder in one stage should connect to the enable of the another decoder in the next stage
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© Mark Redekopp, All rights reserved Cascading Decoders Connect outputs of first stage to enables of next stage Usually, MSB‟s are connected to the first stage, LSB‟s to the following stages Stage 1 Stage 2 Overall Enable 2-to-4 decoder MSB in connects to 1 st stage 4 ouputs D 0 D 1 A E D 0 D 1 A E D 0 D 1 A E X Y Y E D 0 D 1 D 2 D 3
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© Mark Redekopp, All rights reserved Cascading Decoders To understand how this works think of the process of elimination Given a 2-bit number X,Y (X = MSB) If I tell you X=1, what are the possible numbers we can have…2 or 3 If I then tell you Y=0, then you know the number is 2 By decoding one bit at a time we can eliminate half of the possibilities until we get down to the actual number
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© Mark Redekopp, All rights reserved Cascading Decoders E X Y D0 D1 D2 D3 0 x x 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 D 0 D 1 A E D 0 D 1 A E D 0 D 1 A E X=1 Y=0 Y=0 E=1 D 0 D 1 D 2 D 3 Example: X=1,Y=0 = 0 = 0 = 1 = 0 0 1 w/ X=1 we can narrow it down to D 2 or D 3 …and you see that the lower decoder in the second stage is the one that is enabled
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© Mark Redekopp, All rights reserved Cascading Decoders E X Y D0 D1 D2 D3 0 x x 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 D 0 D 1 A E D 0 D 1 A E D 0 D 1 A E X=1 Y=0 Y=0 E=1 D 0 D 1 D 2 D 3 Example: X=1,Y=0 = 0 = 0 = 1 = 0 0 1 The top decoder is disabled so its outputs are forced to 0 The bottom decoder decodes the Y bit and outputs its D 0 (really D 2 )
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© Mark Redekopp, All rights reserved Rules for Making Larger Decoders Rule 1: Outputs of one stage should connect to the enables of the next stage Rule 2: All decoders in a stages should decode the same bit(s) Usually, the MSB is connected to the first stage and LSB to the last stage
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© Mark Redekopp, All rights reserved Cascading Decoders G A 2 A 1 A 0 Active Output 0 X X X None 1 0 0 0 D 0 1 0 0 1 D 1 1 0 1 0 D 2 1 0 1 1 D 3 1 1 0 0 D 4 1 1 0 1 D 5 1 1 1 0 D 6 1 1 1 1 D 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Once a decoder gets disabled all the following will be disabled D 0 D 1 A E D 0 D 1 A E D 0 D 1 A E D 0 D 1 A E D 0 D 1 A E D 0 D 1 A E D 0 D 1 A E A 0 A 1 A 2 G D 0 D 1 D 2 D 3 D 4 D 6 D 5 D 7 A 1 A 1 A 0 A 0 A 0 A 0 A 2
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© Mark Redekopp, All rights reserved Cascading Decoders G A 2 A 1 A 0 Active Output 0 X X X None 1 0 0 0 D 0 1 0 0 1 D 1 1 0 1 0 D 2 1 0 1 1 D 3 1 1 0 0 D 4 1 0 1 D 5 1 1 0 D 6 1 1 1 D 7 1 0 1
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This note was uploaded on 12/02/2009 for the course EE 101 at USC.

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EE101Lecture11 - Introduction to Digital Logic Lecture 11:...

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