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EE101Lecture19

EE101Lecture19 - Introduction to Digital Logic Lecture 19...

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© Mark Redekopp, All rights reserved Introduction to Digital Logic Lecture 19: Flip-Flops
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© Mark Redekopp, All rights reserved Flip-Flops vs. Latches Flip-Flops Synchronous Clock Input Edge-Sensitive Outputs change only on the positive (negative) edges Latches Asynchronous Clock/Enable input Level Sensitive Outputs can change anytime Clock = 1 Bistables Asynchronous No clock input S CLK Q Q R S Q R Q S C Q R Q
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© Mark Redekopp, All rights reserved Master-Slave D-FF One way to build a D-FF is to take 2 D-Latches and chain them together Let the clock go directly to one D-FF but be inverted into the other These are latches NOT FF’s…together they form a D -FF The Master Latch gets the clock directly, the Slave gets the inverse of the clock D C Q Clock Q Q D C Q Q Q D Master Slave
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© Mark Redekopp, All rights reserved Master-Slave D-FF First latch is referred to as master and second is referred to as slave because the input to the slave is the output of the master The slave can only pass what the master “gives” it Q Master = D Slave D C Q Clock Q Q D C Q Q Q D Master Slave
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© Mark Redekopp, All rights reserved Master-Slave D-FF Important: When Clock = 0 => Master = Hold mode, Slave = Transparent When Clock = 1 => Master = Transparent, Slave = Hold Mode C = 0: Hold Transp. C = 1: Transp. Hold D C Q Clock Q Q D C Q Q Q D Master Slave
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© Mark Redekopp, All rights reserved CLK D Q Master Q Slave Master-Slave D-FF CLK = 0: Master Holds, Slave Passes Q Master 0 1 0 D C Q Clock Q Q D C Q Q Q D Master Slave
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© Mark Redekopp, All rights reserved CLK D Q Master Q Slave Master-Slave D-FF CLK = 1: Master Passes D, Slave remembers its last value, 0 1 0 1 D C Q Clock Q Q D C Q Q Q D Master Slave
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© Mark Redekopp, All rights reserved CLK D Q Master Q Slave Master-Slave D-FF CLK = 0: Master remembers the last value,1 Slave Passes Q Master 0 1 0 D C Q Clock Q Q D C Q Q Q D Master Slave
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