EE101Lecture23

EE101Lecture23 - Mark Redekopp, All rights reserved Lecture...

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Unformatted text preview: Mark Redekopp, All rights reserved Lecture 23 Slides Registers Register w/ Enables Counters Mark Redekopp, All rights reserved Registers A Register is a group of D- FFs tied to a common clock and clear (reset) input. Used to store multiple bit values on each clock cycle 4-bit Register CLK /AR D i Q i * X X 1,0 1 X Q i 1 1 1 1 D Q CLR SET /AR D Q CLR SET D Q CLR SET D Q CLR SET 1 1 1 1 CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 Mark Redekopp, All rights reserved Registers Whatever the D value is at the clock edge is sampled and passed to the Q output until the next clock edge 4-bit Register On clock edge, D is passed to Q CLK /AR D[3:0] Q[3:0] 0000 0011 0100 0101 0110 0111 1000 1001 1010 0010 0011 0100 0101 0110 0111 1000 1001 Mark Redekopp, All rights reserved Registers w/ Enables Registers (D- FFs) will sample the D bit every clock edge and pass it to Q Sometimes we may want to hold the value of Q and ignore D even at a clock edge We can add an enable input and...
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EE101Lecture23 - Mark Redekopp, All rights reserved Lecture...

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