EE101Lecture23

EE101Lecture23 - © Mark Redekopp All rights reserved...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: © Mark Redekopp, All rights reserved Lecture 23 Slides Registers Register w/ Enables Counters © Mark Redekopp, All rights reserved Registers • A Register is a group of D- FF’s tied to a common clock and clear (reset) input. • Used to store multiple bit values on each clock cycle 4-bit Register CLK /AR D i Q i * X X 1,0 1 X Q i ↑ 1 ↑ 1 1 1 D Q CLR SET /AR D Q CLR SET D Q CLR SET D Q CLR SET 1 1 1 1 CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 © Mark Redekopp, All rights reserved Registers • Whatever the D value is at the clock edge is sampled and passed to the Q output until the next clock edge 4-bit Register – On clock edge, D is passed to Q CLK /AR D[3:0] Q[3:0] 0000 0011 0100 0101 0110 0111 1000 1001 1010 0010 0011 0100 0101 0110 0111 1000 1001 © Mark Redekopp, All rights reserved Registers w/ Enables • Registers (D- FF’s) will sample the D bit every clock edge and pass it to Q • Sometimes we may want to hold the value of Q and ignore D even at a clock edge • We can add an enable input and...
View Full Document

This note was uploaded on 12/02/2009 for the course EE 101 at USC.

Page1 / 10

EE101Lecture23 - © Mark Redekopp All rights reserved...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online