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VerilogDiscussion - Verilog HDL Mark Redekopp Mark Redekopp...

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© Mark Redekopp, All rights reserved Verilog HDL Mark Redekopp
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© Mark Redekopp, All rights reserved Purpose • HDL‟s were originally used to model and simulate hardware before building it • In the past 15-20 years, synthesis tools were developed that can essentially build the hardware from the same description
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© Mark Redekopp, All rights reserved Differences from Software Software programming languages are inherently sequential Operations executed in sequential order (next, next, next) Hardware blocks always run in parallel (at the same time) Uses event-driven paradigm (change in inputs causes expression to be evaluated) f = a & b; g = a | b; var = x+y; tmp = d-c; Software Perform x+y and when that is done assign d-c to tmp Hardware This description models 2 gates working at the same time Event Driven Paradigm: If a or b changes, f and g will be re-evaluated
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© Mark Redekopp, All rights reserved Modules • Each Verilog designs starts as a block diagram (called a “module” in Verilog) • Start with input and output signals, then describe how to produce outputs from inputs module m1(x,y,z,f,g); // circuit // description endmodule Software analogy: Modules are like functions, but also like classes in that they are objects that you can instantiate multiple times. Module x y z[2:0] f g
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© Mark Redekopp, All rights reserved Ports Input and output signals of a module are called “ports” (similar to parameters/arguments of a software function) Unlike software, ports need to be declared as “input” or “output” Vectors declared using [MSB : LSB] notation Module module m1( x,y,z,f,g ); input x,y; input [2:0] z; output f; output [1:0] g; endmodule x y z[2:0] f g[1:0] These are the ports
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© Mark Redekopp, All rights reserved Signal Types Signals represent the inputs, outputs, and internal values Signals need to be typed Similar to variables in software (e.g. int, char) 2 basic types Wire : Represents a node connecting two logic elements Only for modeling combinational logic Used in “assign” statements and connecting inputs/outputs of modules (structural modeling) Reg (ister): Used for signals that are described behaviorally Used to model combinational & sequential logic Value is retained until changed by another assignment Used for anything produced by an “always” or “initial” block module m1(x,y,z,f,g); input x,y; input [2:0] z output f; output [1:0] g; reg [1:0] g; wire n1, n2; reg n3, n4; ... endmodule Inputs are always type ‘wire’. Outputs are assumed ‘wire’ but can be redefined as ‘reg’
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© Mark Redekopp, All rights reserved Constants Multiple bit constants can be written in the form: – [size] `base value size is number of bits in constant base is o or O for octal, b or B for binary, d or D for decimal, h or H
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VerilogDiscussion - Verilog HDL Mark Redekopp Mark Redekopp...

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