VerilogLecture2

VerilogLecture2 - © Mark Redekopp, All rights reserved...

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Unformatted text preview: © Mark Redekopp, All rights reserved Verilog HDL Testbenches, Timing, and Synthesis © Mark Redekopp, All rights reserved Testbenches • Generate input stimulus (values) to your design over time • Simulator will run the inputs through the circuit you described and find what the output from your circuit would be • Designer checks whether the output is as expected, given the input sequence • Testbenches instantiate the design/unit under tests as well as code to generate the inputs and possibly automatically checking the results Testbench Module Unit Under Test (UUT) (Your design module) Code to generate input stimulus Inputs Outputs © Mark Redekopp, All rights reserved Testbench Modules • Declared as a module just like the design circuit • No inputs or outputs module my_tb; // testbench code endmodule © Mark Redekopp, All rights reserved Testbench Signals • Declare signals in the testbench for the inputs and outputs of the design under test – Inputs to your design should be declared type „reg‟ in the testbench (since you are driving them and their value should persist until you change them) – Outputs from your design should be declared type „wire‟ since your design is driving them module my_tb; reg x,y,z; wire f,g; endmodule module m1 (x,y,z,f,g) ; input x,y,z; output f,g; ... Unit Under Test Testbench © Mark Redekopp, All rights reserved UUT Instantiation • Instantiate your design module as a component (just like you instantiate a gate in you design) • Pass the input and output signals to the ports of the design • For designs with more than 4 or 5 ports, use named mapping rather than positional mapping module my_tb; reg x,y,z; wire f,g; m1 uut(x,y,z,f,g); /* m1 uut(.x(x), .y(y), .z(z), .f(f), .g(g)); */ endmodule module m1(x,y,z,f,g); input x,y,z; output f,g; ... endmodule Unit Under Test Testbench © Mark Redekopp, All rights reserved Generating Input Stimulus (Values) • Now use Verilog code to generate the input values over a period of time module my_tb; reg x,y,z; wire f,g; m1 uut(x,y,z,f,g); /* m1 uut(.x(x), .y(y), .z(z), .f(f), .g(g)); */ endmodule module m1(x,y,z,f,g); input x,y,z; output f,g; ... endmodule Unit Under Test Testbench © Mark Redekopp, All rights reserved Initial Block Statement • Similar to always block but only executes ONCE at the beginning of simulation – No sensitivity list • Tells the simulator to run this code just once (vs. always block that runs on changes in sensitivity list signals or repeats automatically) • Inside the “initial” block we can write code to generate values for the inputs to our design • Use “begin…end” to bracket the code (similar to { .. } in C or Java) module my_tb; reg x,y,z; wire f,g; m1 uut(x,y,z,f,g); initial begin // input stimulus // code end endmodule Testbench © Mark Redekopp, All rights reserved Assignment Statement • Use „=„ to assign a signal a value – Can assign constants • x = 0; y = 1; – Can assign logical relationships...
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This note was uploaded on 12/02/2009 for the course EE 101 at USC.

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VerilogLecture2 - © Mark Redekopp, All rights reserved...

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