MIPS-multipath - Multicycle Datapath(overview Registers...

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Unformatted text preview: Multicycle Datapath (overview) Registers Read Reg1 A L U Read Reg2 Write Reg Data P C Address Instruction or Data Memory MIPS-lite Multicycle Version A B ALU- Out Instruction Register Data Memory Data Register Read data 1 Read data 2 • One ALU (no extra adders) • One Memory (no separate Imem, Dmem) • New Temporary Registers Multicycle Implementation ° Datapath changes • one memory: both instructions and data (because can access on separate steps ) • one ALU (eliminate extra adders) • extra “invisible” registers to capture intermediate (per-step) datapath results ° Controller changes • controller must fire control lines in correct sequence and correct time ⇒ controller must remember current execution step, advance to next step Multicycle Datapath: Add Multiplexors A L U Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end P C << 2 A B ALU- Out Address Read Data Mem Write Data M D R M u x 25:21 20:16 15:0 0 1M 2 u 3 x M u x M u x M u x IR 4 zero 15:11 Note inputs to multiplexors Datapath + Control Points A L U Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end P C << 2 A B ALU- Out Address Read Data Mem Write Data M D R M u x 25:21 20:16 15:0 0 1M 2 u 3 x M u x M u x M u x IR 4 z 15:11 IorD MemRead MemWrite IRWrite RegDst...
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This note was uploaded on 12/02/2009 for the course CDA 3101 taught by Professor Small during the Spring '08 term at University of Florida.

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MIPS-multipath - Multicycle Datapath(overview Registers...

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