MIPS-Pipelining-1 - Pipelining Chapter 6 Clk Cycle 1...

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Unformatted text preview: Pipelining Chapter 6 Clk Cycle 1 Multiple Cycle Implementation: Ifetch Reg Exec Mem Wr Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Load Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Load Store Pipeline Implementation: Ifetch Reg Exec Mem Wr Store Clk Single Cycle Implementation: Load Store Waste Ifetch R-type Ifetch Reg Exec Mem Wr R-type Cycle 1 Cycle 2 How can we further speedup the processor • Use Pipelining – allows several instructions to overlap in time; different parts of several consecutive instructions are executed simultaneously. Clk Cycle 1 Multiple Cycle Implementation: Ifetch Reg Exec Mem Wr Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Load Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Load Store Pipeline Implementation: Ifetch Reg Exec Mem Wr Store Clk Single Cycle Implementation: Load Store Waste Ifetch R-type Ifetch Reg Exec Mem Wr R-type Cycle 1 Cycle 2 Analogy: Laundry ° Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, fold, and put away A B C D ° Dryer takes 30 minutes ° “Folder” takes 30 minutes ° “Stasher” takes 30 minutes to put clothes into drawers ° Washer takes 30 minutes Sequential Laundry Sequential laundry takes 8 hours for 4 loads T a s k O r d e r B C D A 30 Time 3030 30 30 30 30 30 3030 30 30 3030 30 30 6 PM 7 8 9 10 11 12 1 2 AM Pipelined Laundry Pipelined laundry takes 3.5 hours for 4 loads! T a s k O r d e r B C D A 12 2 AM 6 PM 7 8 9 10 11 1 Time 30 3030 30 30 30 30 General Definitions • Latency : time to completely execute a certain task – Time from when a load is started to the time when it is finished – Instruction latency is time from when instruction starts to time when it finishes....
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This note was uploaded on 12/02/2009 for the course CDA 3101 taught by Professor Small during the Spring '08 term at University of Florida.

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MIPS-Pipelining-1 - Pipelining Chapter 6 Clk Cycle 1...

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