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Assn8Soln - CDA 3101 Assignment 8 Due in class on Thursday...

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CDA 3101 Assignment 8 Due in class on Thursday, Nov. 30 Turn hardcopy in class, stapled, with your name and “CDA 3101 Assignment 8” clearly written on it. Important: For some of the problems below, I have provided figures (Figures 5.28, and 5.38 from the textbook) that you need to make additions/changes to. Use a ruler and a RED pen to make any changes/additions to these figures, so that the changes are clearly visible. In case, you make a mistake, I suggest you start with a clean figure. Also, clearly write (in a numbered list) what changes/additions you have made to the figures and why (Please feel free to use extra pages for this). 1. (22 points) Simulate on the multi-cycle path in Fig. 5.28 of the textbook (and using the FSM in Fig. 5.38 of the textbook) the “beq $t0, $t1, label” instruction with $t0 = $t1 = ABCDEF01 16 , label being the 5 instructions above beq, and the instruction address = 0x00400040. Do this by filling in the following for each of the cycles it takes to complete beq (you can put X for don’t know/don’t care). Provide justification for each value you write below. Cycle 1 Cycle 2 Cycle 3 PC 00400040 16 00400044 16 since the PC is always incremented by 4 bytes after the first cycle. 00400044 16 since nothing changes the PC in the second cycle since PCWrite is false. The branch address doesn’t make it in until the rising edge of the 4 th clock cycle. Data port on MEM 1109FFFA 16 X since MemRead is 0, and thus no data is being read. X since MemRead is 0, and thus no data is being read. IorD 0 from FSM...we do indeed want to select the address from the PC to get an instruction X from FSM since it isn’t listed, and we don’t care what address we send to memory because we’re not using memory X from FSM for same reasons as cycle 2
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IR X since the IR doesn’t get written until the rising
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