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Quiz5Soln

# Quiz5Soln - If the time taken by the EX stage is reduced to...

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CDA3101 Quiz 5 Last Name ____________________ Fall 2006 First Name ____________________ Solutions are in blue. 1. Consider a processor where instruction execution is pipelined and has five stages: IF, ID, EX, MEM and WB. Suppose that the IF and ID stages each take 250 picoseconds, that the EX cycle takes 150 picoseconds, the MEM cycle takes 400 picoseconds, and the WB stage takes 80 picoseconds. (a). What is the instruction execution time or latency for any instruction on this processor? 400*5=2000 picosecond (b). Assuming that the pipeline is always full and no instruction is stalled, what is the throughput (in number of instruction/sec) for this pipeline? 1/ (400*10 -12 )= 2.5*10 9 (ins/sec) (c). If
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Unformatted text preview: If the time taken by the EX stage is reduced to 100 picoseconds, it will improve i. the instruction latency ii. the throughput iii. both latency and throughput 2. Look at the following code and (a). determine where the hazards occur and what type of hazard each is. (b). Also, mention whether a stall is necessary or forwarding will work. or \$t0, \$t1, \$t2 no hazard add \$t4, \$t0, \$t0 data hazard (t0), forwarding (to both inputs of the ALU) and \$t1, \$t3, \$t0 data hazard (t0), forwarding lw \$t5, 0(\$t0) no hazard sw \$t0, 0(\$t5) data hazard(t5), stall and forwarding or IF ID EX MEM WB add IF ID EX MEM WB and IF ID EX MEM WB lw IF ID EX MEM WB stall stall stall stall stall sw IF ID EX MEM WB...
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