project_3_design_review - 18-741 Advanced Computer...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
18-741: Advanced Computer Architecture Instructor: Prof. James Hoe Project 3: Tomasulo’s Algorithm Design Review + Extra Credit Description Name: Kun Gao [email protected] Ippokratis Pandis [email protected] 2 November 2005, Pittsburgh, PA
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Advanced Computer Architecture Project 3 11/2/2005 Page 2 of 7
Background image of page 2
Advanced Computer Architecture Project 3 11/2/2005 Page 3 of 7 Design Review 1. Question 1: Explain how Tomasulo’s Algorithm Avoids WAW, RAW, WAR hazards, If we made the Instruction issue out-of-order, do any of these hazards now exist? Answer As stated in [1], Tomasulo’s algorithm tracks when operands for instructions are available in order to minimize RAW hazards. There are many variations for avoiding RAW hazards, but the key concept is of tracking instruction dependences to allow execution as soon as operands are available. Furthermore, Tomasulo’s algorithm introduces register renaming, to minimize WAW and RAW hazards. The register renaming is achieved by using reservation stations, which buffer the operands of instructions waiting to issue, and by the issue logic. Pending instructions designate the reservation station that will provide their input. When successive writes to a register overlap in execution, only the last one is actually used to update the register. As instructions are issued, the register specifiers for pending operands are renamed to the names of the reservation station, which provides register renaming. Since there can be more reservation stations than real registers, the technique can even eliminate hazards arising from name dependences that could not be eliminated by a compiler. Source operand buffering resolves WAR hazards that arise when the operand is available in the registers. Also, it is possible to eliminate WAR hazards by the renaming of a register together with the buffering of a result until no outstanding references to the earlier version of the register remain. If we made the Instruction issue out-of-order, then the things are getting trickier. In particular, we may have dependencies into the system, and maybe some instructions have been already into the reservation stations whereas other (those that depend on) are even there. So for example, let’s say that we have the following two instructions and we issues them out-of-order: Add r1, r2, r3 Mul r4, r1, r1 In the out-of-order instruction issue scenario, it is possible the FP FU to be able to accept new instructions whereas the Int FU to be full. In this case the second instruction will be issued into the reservation station and the first one won’t. This is a clear RAW hazard, and it is difficult to be resolved by Tomasulo’s algorithm. Similarly, we can get WAW and WAR hazards. Therefore there is a general rule in dynamic scheduled pipeline, which states that all instructions pass through the issue stage in order, so that the correct data flow is maintained. However they can be stalled or bypass each other in the following stages. 2.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 7

project_3_design_review - 18-741 Advanced Computer...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online