EE577a_Lecture_25_111709

EE577a_Lecture_25_111709 - E 577a: Sequential Circuits EE...

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Unformatted text preview: E 577a: Sequential Circuits EE 577a: Sequential Circuits November 17, 2009 Background and challenges emory elements/sequencing elements emory elements/sequencing elements Memory elements/sequencing elements Memory elements/sequencing elements – Flipflops Flipflops and latches and latches A A flipflop flipflop is an edge is an edge-triggered memory element triggered memory element – New value applied at output at a clock edge New value applied at output at a clock edge A latch is a level A latch is a level-sensitive sensitive memory element memory element – New value/signal New value/signal is transmitted is transmitted to output when to output when the clock is transparent the clock is transparent Latch Latch-based pipelines based pipelines – More difficult to design and verify than FF More difficult to design and verify than FF-based designs based designs – Allows Allows time borrowing time borrowing (1) (1) Higher Higher performance performance (2) (2) Higher Higher yield yield Latch Latch-based circuits used in full based circuits used in full-custom high custom high-speed circuits, especially speed circuits, especially in highly delay in highly delay-critical parts critical parts 3 Time borrowing in latch Time borrowing in latch-based circuits based circuits L 1 L 4 L 7 C L 2 L C 1 L 5 L L 8 L 3 clk clk clk clk 6 9 clk clk 1 10 20 20 clk clk clk clk Nominal delay for C Nominal delay for C 4 Positive latches (active Positive latches (active-high) high) Nominal delay for each block: T/2 Nominal delay for each block: T/2 = 10 = 10 (T: clk period (T: clk period) Time borrowing in latch Time borrowing in latch-based circuits based circuits L 1 L 4 L 7 C L 2 L C 1 L 5 L L 8 L 3 clk clk clk clk 6 9 clk clk 1 10 20 20 clk clk clk clk ime borrowing (TB): ime borrowing (TB): pplies a new pplies a new alue at an alue at an Nominal delay for C Nominal delay for C 5 Time borrowing (TB): Time borrowing (TB): C 0 0 applies a new applies a new value at an value at an input of input of C 1 after after rising edge of rising edge of clk clk Time borrowing occurs at L Time borrowing occurs at L 5 L 1 L 4 L 7 C L 2 L C 1 L 5 L L 8 L 3 6 9 clk clk clk clk clk clk 1 10 20 20 clk clk clk clk Delay = 12 Delay = 12 orst case nominal delay at output L orst case nominal delay at output L f C f C = 12 = 12 6 Worst case nominal delay at output L Worst case nominal delay at output L 5 of C of C 12 12 May be May be intentional intentional TB TB (by design) (by design) or or unintentional TB unintentional TB (by defects and/or variations) (by defects and/or variations) When to apply inputs & capture responses? C L 3 L 4 C 1 L 6 L 7 C 2 L 9 L 10 L L 1 L 5 L 8 L 11 L 2 clk clk clk clk clk clk “pass” “fail” Apply earliest – at rising edge of clk With respect to the earliest – at rising edge of clk – All chips with time borrowing may seem to “fail” – But may actually “pass” 7 • Depending on delays of multi-segment paths in C +C 1 or C +C 1 +C 2 When to apply inputs & capture responses?When to apply inputs & capture responses?...
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This note was uploaded on 12/03/2009 for the course EE 577A at USC.

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EE577a_Lecture_25_111709 - E 577a: Sequential Circuits EE...

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