Binder3

Binder3 - Boundary Scan The following set of slides are...

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Unformatted text preview: Boundary Scan The following set of slides are courtesy of Professors Niraj Jha and Sandeep Gupta circa 2004 Boundary scan • Boundary scan used to test – Chips-on-board (COB) systems, where chips are mounted on a printed circuit board (PCB) – Multi-chip modules (MCM), where bare-die are integrated on a silicon or a PCB-like substrate Boundary scan • A COB system is obtained by – Using a PCB that contains traces, i.e., metal connectors that constitute inter-chip interconnects, and – Bonding (e.g., soldering) chips on the PCB Boundary scan • Each chip used in a PCB is pretested by the chip’s vendor and declared fault-free • Testing at board level focuses on – Inter-chip interconnect faults • Opens – Caused when chip pins do not bond properly to board – That occur in PCB traces due to defects during PCB manufacturing • Shorts caused when extra solder flows between pins or PCB traces Boundary scan • Testing at board level focuses on – Faults internal to chips • Faults induced due to improper handling, e.g., excessive heat or shock during PCB assembly • Faulty behaviors that become apparent only when a chip is integrated into a PCB, e.g., the ability to drive a large load • These defects – More likely to occur in pad drivers and pad receivers – However, may also occur in system logic , i.e., on-chip logic circuit • Since repair possible, diagnosis also important Boundary scan • Board-level DFT supports – Testing and diagnosis of faults in inter-chip interconnects (including pad drivers and receivers) – In-situ re-testing of system logic – Debugging of system design Boundary scan • Possible approaches for board testing – Consider the entire board as one circuit and generate tests: Not possible because • The circuit too large for ATPG tools • Net-list of most chips unavailable – In-circuit testing • Probes were used to access input/output pins of chips • Care had to be taken to ensure probes driving values did not damage output pins • No longer used because – Pins are too small and too close to be reliably probed – Pins at bottoms of chips cannot be probed in multi-layered PCBs – Boundary scan Boundary scan • Boundary scan incorporates DFT circuitry that allows direct access to chip input and output pins via scan chains • Consider an example board – Especially note • Bi-directional driver/receiver – Pin 3 of Chip 1 • Tri-state driver – Pin 2 of Chip 2 Boundary scan 1 2 3 1 2 3 4 Chip 1 Chip 2 x 1 x 2 x 1 z 5 z 4 z 1 z 1 z 4 z 3 z 2 Board An I/O pin A power/ground pin Edge connector On-chip system logic b 1 b 2 Boundary scan • Assume that – A receiver disconnected from its drivers due to opens interprets the input as having a value 1 – A control value 1 enables a tri-state/bi-directional driver • To test for an open at the simple receiver on net b 1 – Use a probe to apply 0 at Pin 2 of Chip 2 – Use another probe to observe the value at Pin 3 of Chip 1 and Pin 1 of Chip 2...
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Binder3 - Boundary Scan The following set of slides are...

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