Binder2

Binder2 - 1149.1 Boundary Scan Standard Chip Level Architecture BA November 2004 Boundary-Scan Technology Extract from Extract from An Introduction

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1149.1 Boundary Scan Standard: Chip Level Architecture November, 2004 © Bennetts Associates, 2004 Page 1 Slide 1 © 2004, Bennetts Associates 1149-1-chip.ppt, Last revised: November 2004 A B Boundary-Scan Technology Extract from: An Introduction to the IEEE 1149.1 Boundary-Scan Standard Extract from: An Introduction to the IEEE 1149.1 Boundary-Scan Standard A Class Presented By Dr R G “Ben” Bennetts, DFT Consultant Bennetts Associates, UK Tel: +44 1489 581276 E-mail: [email protected] http://www.dft.co.uk/ In this tutorial, you will learn the basic elements of boundary-scan architecture — where it came from, what problem it solves, and the implications on the design of an integrated- circuit device.
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1149.1 Boundary Scan Standard: Chip Level Architecture November, 2004 © Bennetts Associates, 2004 Page 2 Slide 2 © 2004, Bennetts Associates 1149-1-chip.ppt, Last revised: November 2004 A B Use of The “Capture 01” Feature ± Problem: how to “test the tester” i.e. chip-to-chip TDO-to-TDI, plus TMS and TCK connections …01 123 TDO TDI TMS TCK TRST* In an earlier section, we discussed the capture of the fixed 01 pattern into the least two significant positions of the Instruction scan register. Normally, we would think only of shift and update operations for the Instruction register. The question arises — what is the use of the capture 01 pattern? To answer this question, we need to think about the use of the boundary-scan registers at the board level. Consider again the circuit shown above. Previously, we saw how to set up a test environment preparatory to carrying out interconnect tests. To do this, we made use of the test infrastructure i.e., the on-chip boundary-scan features plus the board-level TMS and TCK connections and the chip-to-chip TDO-to-TDI interconnects. It is important to know that this infrastructure is fault-free before making use of it. In other words, we must first test the tester before using the tester to test other parts of the board. This is the purpose of the Instruction register capture 01 operation. Essentially, what happens is as follows: (see next slide also) Step 1: Assuming all devices start in their Test-Logic-Reset state (TMS = 1, 5 x TCK cycle), apply the sequence 0110 to TMS to cause each device to place its Instruction register between TDI and TDO. At this stage, there is a serial shift register that starts at the board TDI and ends at the board TDO and which is made up of the various Instruction registers in the devices — an Instruction register chain. Step 2: Apply an additional sequence to TMS to cause each Instruction register to capture the hardwired 01 into the least two significant positions of each Instruction scan register. Higher-order bits capture what they are set up to capture. These values are not mandated by the Standard. The captured 01 values constitute a checkerboard flush test for the serial Instruction register chain.
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Binder2 - 1149.1 Boundary Scan Standard Chip Level Architecture BA November 2004 Boundary-Scan Technology Extract from Extract from An Introduction

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