Binder0

Binder0 - Melvin A. Breuer 1 8/05; rev. 8/06, 8/07, 8/09...

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Unformatted text preview: Melvin A. Breuer 1 8/05; rev. 8/06, 8/07, 8/09 Introduction to testing of digital circuits and systems University of Southern California Viterbi School of Engineering Ming Hsieh Department of Electrical Engineering Melvin A. Breuer EE658 Fall 2009 Melvin A. Breuer 2 8/05; rev. 8/06, 8/07, 8/09 Key to slides Question : try to answer this question before class Fill-in : copy the answer here _________ from my presentation. This is to help you focus on the material and to attend class Only : slides that you do not have Animation : reminder for me Read only : not discussed in class Melvin A. Breuer 3 8/05; rev. 8/06, 8/07, 8/09 What you should get from this lecture A good idea of the subject matter of this course The importance of VLSI test Basic terminology and concepts related to VLSI test How this material fits into the VLSI/CAD curricula What type of instructor I might be Whether you might like the course material Melvin A. Breuer 4 8/05; rev. 8/06, 8/07, 8/09 Outline for this module The VLSI fabrication process Defects Process variation Errors in computation Yield Burn-in Wafer testing Testing Introduction Modeling defects as faults Quality of a test Generating and applying a test Three test methods Testing in the field Summary Melvin A. Breuer 5 8/05; rev. 8/06, 8/07, 8/09 Outline The VLSI fabrication process Defects Process variation Errors in computation Yield Burn-in Wafer testing Testing Introduction Modeling defects as faults Quality of a test Generating and applying a test Three test methods Testing in the field Summary Melvin A. Breuer 6 8/05; rev. 8/06, 8/07, 8/09 Building circuitry Layer-by-layer Murphy Murphy ’s Law s Law If anything can go wrong, it will. If anything can go wrong, it will. Currently about 6 layers of metal Currently about 6 layers of metal 20-30 masks 20-30 masks Some problem areas: Some problem areas: Planarization Planarization is difficult-need filler is difficult-need filler in empty spaces in empty spaces Add 10 more items to this list Add 10 more items to this list Melvin A. Breuer 7 8/05; rev. 8/06, 8/07, 8/09 A survey Consider a fabrication facility mass producing a large state of the art processor chip using their newest and most advanced xy.z nano-CMOS technology. What fraction of newly manufactured die (chips) are bad and need to be discarded? The boys The girls The MS students The PhD students Melvin A. Breuer 8 8/05; rev. 8/06, 8/07, 8/09 Outline The VLSI fabrication process Defects Process variation Errors in computation Yield Burn-in Wafer testing Testing Introduction Modeling defects as faults Quality of a test Generating and applying a test Three test methods Testing in the field Summary Melvin A. Breuer 9 8/05; rev. 8/06, 8/07, 8/09 Outline The VLSI fabrication process...
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This note was uploaded on 12/03/2009 for the course EE 658 at USC.

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Binder0 - Melvin A. Breuer 1 8/05; rev. 8/06, 8/07, 8/09...

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