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csse232_hw6_soln

csse232_hw6_soln - Fall 2009-2010 CSSE 232 CSSE 232...

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Fall 2009-2010 CSSE 232 CSSE 232 – Computer Architecture I Rose-Hulman Institute of Technology Computer Science and Software Engineering Department Homework 6 Solutions 5.43 (3 points each = 18 points) (a) Divide by zero - Page A-51 of the text describes the MIPS divide instruction. For this instruction, if the value in register rt is zero, this exception will be triggered. In cycle 3 i.e. after the instruction fetch and instruction decode (and pre-fetching of operands into registers A and B) stages, it will be known that the value is register rt is to be used as a divisor and if it is zero, the exception should be triggered. The exception will not be triggered by any of the other instructions. (b) Overflow exception - This can be triggered any time the ALU is used for an add or subtract operation. Depending on implementation, cycles 1 (adding 4 to the PC) and 2 (adding the sign-exnted and shufted 16-bit immediate value from the instruction) of all instructions, cycle 3 of lw and sw (memory address calculation), and cycle 3 of the beq instruction (determine if A - B == 0) may trigger this exception. Cycle 3 of R-type instructions (add, sub) should trigger
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