L18-ac-blocks-latches-6up

L18-ac-blocks-latches-6up - inst.eecs.berkeley.edu/~cs61c...

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CS61C L18 Combinational Logic Blocks, Latches (1) Chae, Summer 2008 © UCB Albert Chae, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #18 – Combinational Logic Blocks, Latches 2008-7-22 CS61C L18 Combinational Logic Blocks, Latches (2) Chae, Summer 2008 © UCB Review Use this table and techniques we learned to transform from 1 to another CS61C L18 Combinational Logic Blocks, Latches (3) Chae, Summer 2008 © UCB Today Common Combinational Logic Blocks Data Multiplexors Arithmetic and Logic Unit Adder/Subtractor CS61C L18 Combinational Logic Blocks, Latches (4) Chae, Summer 2008 © UCB Data Multiplexor (here 2-to-1, n-bit-wide) “mux” CS61C L18 Combinational Logic Blocks, Latches (5) Chae, Summer 2008 © UCB N instances of 1-bit-wide mux How many rows in TT? CS61C L18 Combinational Logic Blocks, Latches (6) Chae, Summer 2008 © UCB How do we build a 1-bit-wide mux?
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CS61C L18 Combinational Logic Blocks, Latches (7) Chae, Summer 2008 © UCB 4-to-1 Multiplexor? How many rows in TT? CS61C L18 Combinational Logic Blocks, Latches (8) Chae, Summer 2008 © UCB Is there any other way to do it? Hint: March Madness Ans: Hierarchically! CS61C L18 Combinational Logic Blocks, Latches (9) Chae, Summer 2008 © UCB 0 1 Do you really understand NORs? If one input is 1, what is a NOR ? If one input is 0, what is a NOR ? A B NOR 0 0 1 0 1 0 1 0 0 1 1 0 A B NOR A NOR 0 B 1 0 A _ B 0 NOR CS61C L18 Combinational Logic Blocks, Latches (10) Chae, Summer 2008 © UCB 0 1 Do you really understand NANDs? If one input is 1, what is a NAND ? If one input is 0, what is a NAND ? A B NAND 0 0 1 0 1 1 1 0 1 1 1 0 A NAND 0 1 1 B A 1 _ B NAND A B NAND CS61C L18 Combinational Logic Blocks, Latches (11) Chae, Summer 2008 © UCB Arithmetic and Logic Unit Most processors contain a special logic block called “Arithmetic and Logic Unit” (ALU) We ll show you an easy one that does ADD, SUB, bitwise AND, bitwise OR CS61C L18 Combinational Logic Blocks, Latches (12) Chae, Summer 2008 © UCB Our simple ALU
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CS61C L18 Combinational Logic Blocks, Latches (13) Chae, Summer 2008 © UCB Adder/Subtracter Design -- how? Truth-table, then determine canonical form, then minimize and implement as we ve seen before Look at breaking the problem down into smaller pieces that we can cascade or hierarchically layer CS61C L18 Combinational Logic Blocks, Latches (14) Chae, Summer 2008 © UCB Adder/Subtracter – One-bit adder LSB… CS61C L18 Combinational Logic Blocks, Latches (15) Chae, Summer 2008 © UCB Adder/Subtracter – One-bit adder (1/2)… CS61C L18
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This note was uploaded on 12/06/2009 for the course CS cs61c taught by Professor Cory during the Summer '08 term at Berkeley College.

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L18-ac-blocks-latches-6up - inst.eecs.berkeley.edu/~cs61c...

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