This preview shows pages 1–3. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: CS61C L19 Intro to CPU (1) Chae, Summer 2008 UCB Albert Chae, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #19 Intro to CPU Design 2008-7-23 CS61C L19 Intro to CPU (2) Chae, Summer 2008 UCB Review Use muxes to select among input S input bits selects 2 S inputs Each input can be n-bits wide, indep of S Can implement muxes hierarchically ALU can be implemented using a mux Coupled with basic block elements N-bit adder-subtractor done using N 1- bit adders with XOR gates on input XOR serves as conditional inverter Latches are used to implement Fip- Fops CS61C L19 Intro to CPU (3) Chae, Summer 2008 UCB ive Components of a Computer Processor Computer Control Datapath Memory (passive) (where programs, data live when running) Devices Input Output Keyboard, Mouse Display , Printer Disk (where programs, data live when not running) CS61C L19 Intro to CPU (4) Chae, Summer 2008 UCB The CPU Processor (CPU): the active part of the computer, which does all the work (data manipulation and decision- making) Datapath : portion of the processor which contains hardware necessary to perform operations required by the processor (the brawn) Control : portion of the processor (also in hardware) which tells the datapath what needs to be done (the brain) CS61C L19 Intro to CPU (5) Chae, Summer 2008 UCB Stages of the Datapath : Overview Problem: a single, atomic block which executes an instruction (performs all necessary operations beginning with fetching the instruction) would be too bulky and inefcient Solution: break up the process of executing an instruction into stages, and then connect the stages to create the whole datapath smaller stages are easier to design easy to optimize (change) one stage without touching the others CS61C L19 Intro to CPU (6) Chae, Summer 2008 UCB Stages of the Datapath (1/5) There is a wide variety of MIPS instructions: so what general steps do they have in common? Stage 1: Instruction etch no matter what the instruction, the 32-bit instruction word must rst be fetched from memory (the cache-memory hierarchy) also, this is where we Increment PC (that is, PC = PC + 4, to point to the next instruction: byte addressing so + 4) CS61C L19 Intro to CPU (7) Chae, Summer 2008 UCB Stages of the Datapath (2/5) Stage 2: Instruction Decode upon fetching the instruction, we next gather data from the Felds ( decode all necessary instruction data) Frst, read the Opcode to determine instruction type and Feld lengths second, read in data from all necessary registers- for add , read two registers- for addi , read one register- for jal , no reads necessary CS61C L19 Intro to CPU (8) Chae, Summer 2008 UCB Stages of the Datapath (3/5) Stage 3: ALU (Arithmetic-Logic Unit) the real work of most instructions is done here: arithmetic (+, -, *, /), shifting, logic (&, |), comparisons ( slt...
View Full Document
This note was uploaded on 12/06/2009 for the course CS cs61c taught by Professor Cory during the Summer '08 term at Berkeley College.
- Summer '08