L20-ac-datapathII-control

L20-ac-datapathII-control - inst.eecs.berkeley.edu/~cs61c...

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CS61C L20 Single Cycle Datapath, Control (1) Chae, Summer 2008 © UCB Albert Chae, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #20 – Single Cycle CPU Datapath and Control 2008-7-24
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CS61C L20 Single Cycle Datapath, Control (2) Chae, Summer 2008 © UCB Revie w CPU design involves Datapath,Control Datapath in MIPS involves 5 CPU stages 1) Instruction Fetch 2) Instruction Decode & Register Read 3) ALU (Execute) 4) Memory 5) Register Write
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CS61C L20 Single Cycle Datapath, Control (3) Chae, Summer 2008 © UCB Single Cycle CPU Single Cycle CPU : All stages of an instruction are completed within one long clock cycle. The clock cycle is made sufficient long to allow each instruction to complete all stages without interruption and within one cycle. For each instruction, how do we control the flow of information though the datapath? 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Reg. Write
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CS61C L20 Single Cycle Datapath, Control (4) Chae, Summer 2008 © UCB How to Design a Processor: step-by- step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic
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CS61C L20 Single Cycle Datapath, Control (5) Chae, Summer 2008 © UCB Step 3: Assemble DataPath meeting requirements Register Transfer Requirements Datapath Assembly Instruction Fetch Read Operands and Execute Operation
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CS61C L20 Single Cycle Datapath, Control (6) Chae, Summer 2008 © UCB 3a: Overview of the Instruction Fetch Unit The common RTL operations Fetch the Instruction: mem[PC] Update the program counter: - Sequential Code: PC PC + 4 - Branch and Jump: PC “something else” 32 Instruction Word Address Instruction Memory PC clk Next Address Logic
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CS61C L20 Single Cycle Datapath, Control (7) Chae, Summer 2008 © UCB 3b: Add & Subtract R[rd] = R[rs] op R[rt] Ex.: addU rd,rs,rt Ra, Rb, and Rw come from instruction’s Rs , Rt , and Rd fields ALUctr and RegWr : control logic after decoding the instruction 32 Result ALUctr clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rd ALU op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits Already defined the register file & ALU
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CS61C L20 Single Cycle Datapath, Control (8) Chae, Summer 2008 © UCB Clocking Methodology Storage elements clocked by same edge Being physical devices, flip-flops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-Q delay Critical path ” (longest path through logic) determines length of clock period Clk .
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This note was uploaded on 12/06/2009 for the course CS cs61c taught by Professor Cory during the Summer '08 term at Berkeley College.

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L20-ac-datapathII-control - inst.eecs.berkeley.edu/~cs61c...

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